Cortex-R4 and Cortex-R4F Technical Reference Manual: 4.2. Register summary

4.2. Register summary

The system control coprocessor appears as a set of registers that you can write to and read from. Some of the registers permit more than one type of operation. The functional groups for the registers are:

Table 4.1 shows the overall functionality for the system control coprocessor, provided through the registers. The registers are listed in their functional groups.

Table 4.2 lists the registers in the system control processor, in register order, and gives the reset value for each register.

Table 4.1. System control coprocessor register functions

Function	Register/operation	Reference to description
System identification, control and configuration	Control	c1, System Control Register
	Auxiliary control	c1, Auxiliary Control Register
	Coprocessor Access Control	c1, Coprocessor Access Register
	Main ID^[a]	c0, Main ID Register
	Product Feature IDs	The Processor Feature Registers c0, Debug Feature Register 0 c0, Auxiliary Feature Register 0 Memory Model Feature Registers Instruction Set Attributes Registers
	Multiprocessor ID	c0, Multiprocessor ID Register
	Context ID	c13, Context ID Register
	FCSE PID	c13, FCSE PID Register
	Build Options 1	c15, Build Options 1 Register
	Build Options 2	c15, Build Options 2 Register
Software compatibility	Thread And Process ID	c13, Thread and Process ID Registers
MPU control and configuration	Data Fault Status	c5, Data Fault Status Register
	Auxiliary Fault Status	c5, Auxiliary Fault Status Registers
	Instruction Fault Status	c5, Instruction Fault Status Register
	Instruction Fault Address	c6, Instruction Fault Address Register
	Data Fault Address	c6, Data Fault Address Register
	MPU Type	c0, MPU Type Register
	Region Base Address	c6, MPU Region Base Address Registers
	Region Size and Enable	c6, MPU Region Size and Enable Registers
	Region Access Control	c6, MPU Region Access Control Registers
	Memory Region Number	c6, MPU Memory Region Number Register
	Correctable Fault Location register	Correctable Fault Location Register
Cache control and configuration	Cache Type	c0, Cache Type Register
	Current Cache Size Identification	c0, Current Cache Size Identification Register
	Current Cache Level	c0, Current Cache Level ID Register
	Cache Size Selection	c0, Cache Size Selection Register
	c7, Cache Operations	Cache operations
	c15, Invalidate all data cache	Cache operations
Interface control and configuration	TCM Status	c0, TCM Type Register
	Region	c9, BTCM Region Register c9, TCM Selection Register
	Slave Port Control	c11, Slave Port Control Register
System performance monitoring	Performance monitoring	Chapter 6 Events and Performance Monitor
Validation	System validation	Validation Registers
^[a]Known as the ID Code Register on previous designs. Returns the device ID code.

Copyright © 2006-2011 ARM Limited. All rights reserved.	ARM DDI 0363G
Non-Confidential	ID041111
PDF version