4.3.31. Build Options Registers

Note

These registers are implemented from the r1pn releases of the processor. Attempting to access these registers in r0pn releases of the processor results in an Undefined Instruction exception.

c15, Build Options 1 Register

The Build Options 1 Register characteristics are:

Purpose

Reflects the build configuration options used to build the processor.

Usage constraints

The Build Options 1 Register is:

  • a read-only register

  • accessible in Privileged mode only

Configurations

Available in all processor configurations.

Attributes

Figure 4.54 shows the Build Options 1 Register bit assignments.

Figure 4.54. Build Options 1 Register bit assignments

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Table 4.56 shows the Build Options 1 Register bit assignments.

Table 4.56. Build Options 1 Register bit assignments

BitsNameFunction
[31:12]TCM_HI_INIT_ADDRDefault high address for the TCM.
[11:0]-SBZ

To access the Build Options 1 Register, read CP15 with:

MRC p15, 0, <Rd>, c15, c2, 0 ; read Build Options 1 Register 

c15, Build Options 2 Register

The Build Options 2 Register characteristics are:

Purpose

Reflects the build configuration options used to build the processor.

Usage constraints

The Build Options 2 Register is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.55 shows the Build Options 2 Register bit assignments.

Figure 4.55. Build Options 2 Register bit assignments

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Table 4.57 shows the Build Options 2 Register bit assignments.

Table 4.57. Build Options 2 Register bit assignments

BitsNameFunction
[31]DUAL_CORE[a]

Indicates whether a second, redundant, copy of the processor logic and checking logic was instantiated:

0 = single core

1 = dual core.

[30]DUAL_NCLK[a]

Indicates whether an inverted clock is used for the redundant core:

0 = inverted clock not used

1 = inverted clock used.

[29]NO_ICACHE

Indicates whether the processor contains instruction cache:

0 = processor contains instruction cache

1 = processor does not contain instruction cache.

[28]NO_DCACHE

Indicates whether the processor contains data cache:

0 = processor contains data cache

1 = processor does not contain data cache.

[27:26]ATCM_ES

Indicates whether an error scheme is implemented on the ATCM interface:

00 = no error scheme

01 = 8-bit parity logic

10 = 32-bit error detection and correction

11 = 64-bit error detection and correction.

[25:24]BTCM_ES

Indicates whether an error scheme is implemented on the BTCM interface(s):

00 = no error scheme

01 = 8-bit parity logic

10 = 32-bit error detection and correction

11 = 64-bit error detection and correction.

[23]NO_IE

Indicates whether the processor supports big-endian instructions:

0 = processor supports big-endian instructions

1 = processor does not support big-endian instructions.

[22]NO_FPU

Indicates whether the processor contains a floating point unit:

0 = processor contains a floating point unit

1 = processor does not contain a floating point unit.

[21]NO_MPU

Indicates whether the processor contains a Memory Protection Unit (MPU):

0 = processor contains an MPU

1 = processor does not contain an MPU.

[20]MPU_REGIONS

Indicates the number of regions in the included MPU:

0 = 8

1 = 12.

If the processor does not contain an MPU (bit [21] set to 0), this bit is set to 0.

[19:17]BREAK_POINTS

Indicates the number of break points implemented in the processor, minus 1.

[16:14]WATCH_POINTS

Indicates the number of watch points implemented in the processor, minus 1.

[13]NO_A_TCM_INF

Indicates whether the processor contains an ATCM port:

0 = processor contains ATCM port

1 = processor does not contain ATCM port.

[12]NO_B0_TCM_INF

Indicates whether the processor contains a B0TCM port:

0 = processor contains B0TCM port

1 = processor does not contain B0TCM port.

[11]NO_B1_TCM_INF

Indicates whether the processor contains a B1TCM port:

0 = processor contains B1TCM port

1 = processor does not contain B1TCM port.

[10]TCMBUSPARITY

Indicates whether the processor contains TCM address bus parity logic:

0 = processor does not contain TCM address bus parity logic

1 = processor contains TCM address bus parity logic.

[9]NO_SLAVE

Indicates whether the processor contains an AXI slave port:

0 = processor contains an AXI slave port

1 = processor does not contain an AXI slave port.

[8:7]ICACHE_ES

Indicates whether an error scheme is implemented for the instruction cache:

00 = no error scheme

01 = 8-bit parity error detection

11 = 64-bit error detection and correction.

If the processor does not contain an Icache, these bits are set to 00.

[6:5]DCACHE_ES

Indicates whether an error scheme is implemented for the data cache:

00 = no error scheme

01 = 8-bit parity error detection

10 = 32-bit error detection and correction.

If the processor does not contain a Dcache, these bits are set to0b00.

[4]NO_HARD_ERROR_CACHE

Indicates whether the processor contains cache for corrected TCM errors:

0 = processor contains TCM error cache

1 = processor does not contain TCM error cache.

[3]AXIBUSPARITY

Indicates whether the processor contains AXI bus parity logic.

0 = processor does not contain AXI bus parity logic

1 = processor contains AXI bus parity logic.

[2:0]-Undefined.

[a] The value of this bit is Unpredictable in revision r1p0 of the processor.


To access the Build Options 2 Register, write CP15 with:

MRC p15, 0, <Rd>, c15, c2, 1 ; read Build Options 2 Register 
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