Appendix E. Revisions

This appendix describes the technical changes between released issues of this book.

Table E.1. Differences between issue B and issue C

ChangeLocation
Added dormant mode description

Power management

Clarified the description of Thumb-2 technology and Thumb instructions

Clarified byte-invariant big-endian format Byte-invariant big-endian format
Clarified little-endian formatLittle-endian format
nCPUHALT removed from timing diagramFigure 4.1
Added sections

Updated reset value information for:

  • Cache Type Register

  • MPU Type Register

  • Instruction Set Attributes Register 1

  • Instruction Set Attributes Register 4

  • Current Cache Size Identification Register

  • Current Cache Level ID Register

  • MPU Region Base Address Registers

  • MPU Region Size and Enable Register

  • MPU Region Access Control Register

  • MPU Memory Region Number

  • ATCM Region Register

  • BTCM Region Register

  • TCM selection Register

  • Performance Monitor Control Register

  • Software Increment Register

  • User read/write Thread and Process ID Register

  • User read-only Thread and Process ID Register

  • Privileged-only Thread and Process ID Register

  • Secondary Auxiliary Control Register

  • Build Options 1 Register

  • Build Options 2 Register

  • Correctable Fault Location Register

Table 4.2
Updated Type information for the CPACRTable 4.2

Clarified the description of the Instruction Set Attributes Register 3

Clarified functions for bits [31], [30], [29], and 28]Table 4.24
Clarified functions for bits [20], [19], [18], [17], [16], [3], and [2]Table 4.25
Clarified instructions that the PFU recognizes as procedure calls and procedure returns

Return stack

Added reference to Application Note 204Memory types
Added sectionUsing memory types
Clarified the description of region attributesRegion attributes
Clarified the description of store buffer drainingStore buffer draining
Clarified the encodings for some signalsAXI master interface
Clarified the number of Identifiers used for AXI bus accessesIdentifiers for AXI bus accesses
Clarified the description of the handling of TCM external faultsExternal TCM errors
Added section

Dormant mode

Updated the permitted instruction combinationsTable C.28
Updated the descriptions for COMMRX and COMMTX signalsTable A.13

Table E.2. Differences between issue C and issue D

ChangeLocation
No technical changes. Removal of access restriction only.-

Table E.3. Differences between issue D and issue E

ChangeLocation
Clarified the description of Abort Handler.Abort handler.

Updated reset value of cache type register.

Table 4.2.
Updated Cache Type Register bit [14].Figure 4.8.
Updated description of Cache Type Register bits [15:14].Table 4.4.
Updated System Control Register bit [21].Figure 4.26.

Clarified note about Auxiliary Control Register bit [12] and description of bits [27:26].

Table 4.24.
Clarified note about Secondary Auxiliary Control Register bit [21].Table 4.25.
Clarified function description of MPU Region Access Control Register bits [1:0].Table 4.33.
Added paragraph to clarify the error correction method used.Error correction.
Clarified description of using semaphores.
Updated combined issuing capability value for AXI master interface.Table 9.1.
Clarified description of ARADDRS[22:3].TCM RAM access.
Updated ReadDCC() code.Example 12.4.
Updated PollDCC() code.Example 12.6.
Updated reset value of MVFR1Table 11.1.
Updated instruction descriptions to comply with the ARM Architecture Reference Manual.Appendix C Cycle Timings and Interlock Behavior.
Clarified configuration signal descriptions and added references where appropriate.Table A.2.
Revised value of ATCACCTYPE[2:0], B1TCACCTYPE[2:0], and B0TCACCTYPE[2:0] signals for MBIST accesses. Also added footnote to clarify MBIST TCM access behavior.

Table E.4. Differences between issue E and issue F

ChangeLocation
No technical changes-

Table E.5. Differences between issue F and issue G

ChangeLocation
Update introductory informationChapter 1 Introduction
Update register descriptions Chapter 3 Programmers Model
Chapter 4 System Control
Chapter 6 Events and Performance Monitor
Chapter 11 FPU Programmers Model
Chapter 12 Debug
Update debug register namesThroughout book
Update undefined instruction exampleUndefined instruction
Update description of L1 memory accessTable 4.34
Update description of Slave Port Control Registerc11, Slave Port Control Register
Update instruction prefetch descriptionControlling instruction prefetch and program flow prediction
Update event bus interface descriptionEvent bus interface
Update description of store buffer drainingStore buffer draining
Update AXI slave interface attributesAXI slave characteristics
Update Cache RAM access descriptionCache RAM access
Update the Revision field of the FPSID registerFloating-Point System ID Register
Update the Revision field of the Peripheral ID Register 2Table 12.35
Remove Programming and reading Integration Test RegistersChapter 13 Integration Test Registers
Update description of ATCEN1 signalTable A.6
Update description of COMMRX and COMMTX Table A.13

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