A.5.4. AXI slave port error detection signals

Table A.7 shows the AXI slave port error detection signals. These signals are only generated if the processor is configured to include AXI bus parity. See Configurable options for more information.

Table A.7. AXI slave port error detection signals

SignalDirectionClockingDescription
AWPARITYSInputCLKINParity bit for write address channel
WPARITYSInputCLKINParity bit for write data channel
BPARITYSOutputCLKINParity bit for write response channel
ARPARITYSInputCLKINParity bit for read address channel
RPARITYSOutputCLKINParity bit for read data channel
AXISPARERR[2:0]OutputCLKINParity error indication for read address, bit [2], write data, bit [1], and write address, bit [0], channels.

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