12.3.4. Memory-mapped registers

Table 12.3 shows the complete list of memory-mapped registers accessible at the APB slave interface.

Note

You must ensure that the base address of this 4KB register map is aligned to a 4KB boundary in physical memory.

Table 12.3. Debug memory-mapped registers

Offset (hex)

Register number

AccessMnemonicDescription
0x000c0RDBGDIDRCP14 c0, Debug ID Register
0x004-0x014c1-c5R-RAZ
0x18c6RWDBGWFARWatchpoint Fault Address Register
0x01Cc7RWDBGVCRVector Catch Register
0x020c8R-RAZ
0x024c9RWDBGECRNot implemented in this processor. Reads as zero.
0x028c10RWDBGDSCCRDebug State Cache Control Register.
0x02Cc11R-

RAZ

0x030-0x07Cc12-c31R-RAZ
0x080c32RWDBGDTRRXData Transfer Register
0x084c33WDBGITRInstruction Transfer Register
0x088c34RWDBGDSCRCP14 c1, Debug Status and Control Register
0x08Cc35RWDBGDTRTXData Transfer Register
0x090c36WDBGDRCRDebug Run Control Register
0x094-0x0FCc37-c63R-RAZ
0x100-0x11Cc64-c71RW DBGBVRBreakpoint Value Registers
0x120-0x13Cc72-c79R-RAZ
0x140-0x15Cc80-c87RWDBGBCRBreakpoint Control Registers
0x160-0x17Cc88-c95R-RAZ
0x180-0x19Cc96-c103RWDBGWVRWatchpoint Value Registers
0x1A0-0x1BCc104-c111R-RAZ
0x1C0-0x1DCc112-c119RWDBGWCRWatchpoint Control Registers
0x1E0-0x1FCc120-c127R-RAZ
0x200-0x2FCc128-c191R-RAZ
0x300c192RDBGOSLAR

Not implemented in this processor. Reads as zero.

0x304c193RDBGOSLSROperating System Lock Status Register
0x308c194RDBGOSSRR

Not implemented in this processor. Reads as zero.

0x30Cc195R-RAZ
0x310c196RWDBGPRCRDevice Power-down and Reset Control Register
0x314c197RDBGPRSRDevice Power-down and Reset Status Register
0x318-0x7FCc198-c511R-RAZ
0x800-0x8FCc512-575R-RAZ
0x900-0xCFCc576-c831R-RAZ
0xD00-0xDFCc832-c895R-Processor ID Registers
0xE00-0xE7Cc896-c927R-RAZ
0xE80-0xEFCc928-c959--Chapter 13 Integration Test Registers
0xF00-0xFFCc960-c1023--Management registers

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