| Copyright © 2006-2011 ARM Limited. All rights reserved. | ARM DDI 0363G |
| Non-Confidential | ID041111 |
 PDF version | |
| Home > Debug > Debug register interface > Memory-mapped registers |
| |||
| Home > Debug > Debug register interface > Memory-mapped registers | |||
Table 12.3 shows the complete list of memory-mapped registers accessible at the APB slave interface.
You must ensure that the base address of this 4KB register map is aligned to a 4KB boundary in physical memory.
Table 12.3. Debug memory-mapped registers
| Offset (hex) | Register number | Access | Mnemonic | Description |
|---|---|---|---|---|
0x000 | c0 | R | DBGDIDR | CP14 c0, Debug ID Register |
0x004-0x014 | c1-c5 | R | - | RAZ |
0x18 | c6 | RW | DBGWFAR | Watchpoint Fault Address Register |
0x01C | c7 | RW | DBGVCR | Vector Catch Register |
0x020 | c8 | R | - | RAZ |
0x024 | c9 | RW | DBGECR | Not implemented in this processor. Reads as zero. |
0x028 | c10 | RW | DBGDSCCR | Debug State Cache Control Register. |
0x02C | c11 | R | - | RAZ |
0x030-0x07C | c12-c31 | R | - | RAZ |
0x080 | c32 | RW | DBGDTRRX | Data Transfer Register |
0x084 | c33 | W | DBGITR | Instruction Transfer Register |
0x088 | c34 | RW | DBGDSCR | CP14 c1, Debug Status and Control Register |
0x08C | c35 | RW | DBGDTRTX | Data Transfer Register |
0x090 | c36 | W | DBGDRCR | Debug Run Control Register |
0x094-0x0FC | c37-c63 | R | - | RAZ |
0x100-0x11C | c64-c71 | RW | DBGBVR | Breakpoint Value Registers |
0x120-0x13C | c72-c79 | R | - | RAZ |
0x140-0x15C | c80-c87 | RW | DBGBCR | Breakpoint Control Registers |
0x160-0x17C | c88-c95 | R | - | RAZ |
0x180-0x19C | c96-c103 | RW | DBGWVR | Watchpoint Value Registers |
0x1A0-0x1BC | c104-c111 | R | - | RAZ |
0x1C0-0x1DC | c112-c119 | RW | DBGWCR | Watchpoint Control Registers |
0x1E0-0x1FC | c120-c127 | R | - | RAZ |
0x200-0x2FC | c128-c191 | R | - | RAZ |
0x300 | c192 | R | DBGOSLAR | Not implemented in this processor. Reads as zero. |
0x304 | c193 | R | DBGOSLSR | Operating System Lock Status Register |
0x308 | c194 | R | DBGOSSRR | Not implemented in this processor. Reads as zero. |
0x30C | c195 | R | - | RAZ |
0x310 | c196 | RW | DBGPRCR | Device Power-down and Reset Control Register |
0x314 | c197 | R | DBGPRSR | Device Power-down and Reset Status Register |
0x318-0x7FC | c198-c511 | R | - | RAZ |
0x800-0x8FC | c512-575 | R | - | RAZ |
0x900-0xCFC | c576-c831 | R | - | RAZ |
0xD00-0xDFC | c832-c895 | R | - | Processor ID Registers |
0xE00-0xE7C | c896-c927 | R | - | RAZ |
0xE80-0xEFC | c928-c959 | - | - | Chapter 13 Integration Test Registers |
0xF00-0xFFC | c960-c1023 | - | - | Management registers |
| Copyright © 2006-2011 ARM Limited. All rights reserved. | ARM DDI 0363G |
| Non-Confidential | ID041111 |
| PDF version | |
| Home > Debug > Debug register interface > Memory-mapped registers |