12.4.5. CP14 c1, Debug Status and Control Register

The DBGDSCR Register characteristics are:

Purpose

Contains status and control information about the debug unit.

Usage constraints
Configurations

Available in all processor configurations.

Attributes

Figure 12.5 shows the DBGDSCR bit assignments.

Figure 12.5. DBGDSCR Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 12.10 shows the DBGDSCR bit assignments.

Table 12.10. DBGDSCR Register bit assignments

BitsNameFunction

[31]

-

RAZ on reads, SBZP on writes.

[30]

DTRRXfull

The DTRRXfull flag:

0 = Read-DTR, DBGDTRRX is empty. This is the reset value

1 = Read-DTR, DBGDTRRX is full.

When set, this flag indicates to the processor that there is data available to read from the DBGDTRRX. It is automatically set on writes to the DBGDTRRX by the debugger, and is cleared when the processor reads the DBGDTRRX over the CP14 interface. If the flag is not set, reads from the DBGDTRRX return an Unpredictable value.

[29]

DTRTXfull

The DTRTXfull flag:

0 = Write-DTR, DBGDTRTX is empty. This is the reset value.

1 = Write-DTR, DBGDTRTX is full.

When clear, this flag indicates to the processor that the DBGDTRTX is ready to receive data. It is automatically cleared on reads of the DBGDTRTX by the debugger, and is set when the processor writes to the DBGDTRTX over the CP14 interface. If this bit is set and the processor attempts to write to the DBGDTRTX, the register contents are overwritten and the DTRRXfull flag remains set.

[28]

-

RAZ on reads, SBZP on writes.

[27]

DTRRXfull_l

The latched DTRRXfull flag. This is the last value of DTRRXfull that the debugger read. It is set to the value of DTRRXfull on a debugger read of the DBGDSCR.

This flag controls how the DBGDTRRX is written by a debugger. See DTR access mode for more information.

The value read for this bit depends on the state of the locked bit in the DBGLSR and the PADDRDBG31 value used for the read. If the locked bit is set, and PADDRDBG31 is 0, then this bit reads as the DTRRXfull_l value. Otherwise it reads as the DTRRXfull value.

[26]

DTRTXfull_l

The latched DTRTXfull flag. This is the last value of DTRTXfull that the debugger read. It is set to the value of DTRTXfull on a debugger read of the DBGDSCR.

This flag controls how the DBGDTRTX is read by the debugger. See DTR access mode for more information.

The value read for this bit depends on the state of the locked bit in the DBGLSR and the PADDRDBG31 value used for the read. If the locked bit is set and PADDRDBG31 is 0, then this bit reads as the DTRTXfull_l value. Otherwise it reads as the DTRTXfull value.

[25]

PipeAdv

Sticky pipeline advance read-only bit. This bit enables the debugger to detect whether the processor is idle. In some situations, this might mean that the system bus port is deadlocked. This bit is set to 1 when the processor pipeline retires one instruction. It is cleared by a write to DBGDRCR[3].

0 = no instruction has completed execution since the last time this bit was cleared

1 = an instruction has completed execution since the last time this bit was cleared.

[24]

InstrCompl_l

The latched instruction complete read-only bit. This flag determines whether the processor has completed execution of an instruction issued by the debugger, through the DBGITR.

0 = processor is executing an instruction fetched from the DBGITR Register

1 = processor is not executing an instruction fetched from the DBGITR Register.

Entry into halting debug state sets this flag to 1. When the processor is not in halting debug state, the value of this flag is Unpredictable. This flag controls debugger writes to the DBGITR:

  • If DBGDSCR[21:20] is equal to 0, then writes to the DBGITR are ignored when InstrCompl_l is 0.

  • If DBGDSCR[21:20] is not equal to 0 then debugger writes to the DBGITR are stalled until InstrCompl_l is 1.

[23:22]

-

RAZ on reads, SBZP on writes.

[21:20]

DTR access

DTR access mode. You can use this field to optimize DTR traffic between a debugger and the processor.

b00 = Non-blocking mode. This is the default.

b01 = Stall mode

b10 = Fast mode

b11 = Reserved.

Note

  • This field only affects the behavior of DBGDSCR, DTR, and DBGITR accesses through the APB port, and not through CP14 debug instructions.

  • Non-blocking mode is the default setting. Improper use of the other modes might result in the debug access bus becoming deadlocked.

See DTR access mode for more information.

[19]

Discard asynchronous abortThis bit controls how the processor handles asynchronous data aborts when in halting debug mode:0 = aborts are handled as normal1 = the sticky asynchronous abort bit is set on an asynchronous abort but no other action is taken.The processor automatically sets this bit on entry into halting debug state and clears it on exit from halting debug state.

[18-16]

-

RAZ on reads, SBZP on writes.

[15]

Monitor mode

The Monitor debug-mode enable bit:

0 = Monitor debug-mode disabled, this is the reset value

1 = Monitor debug-mode enabled.

If Halting debug-mode is enabled through bit [14], then the processor is in Halting debug-mode regardless of the value of bit [15]. If the external interface input DBGEN is LOW, this bit reads as 0. The programmed value is masked until DBGEN is HIGH, and at that time the read value reverts to the programmed value.

[14]Halting mode

The Halting debug-mode enable bit:

0 = Halting debug-mode disabled, this is the reset value

1 = Halting debug-mode enabled.

If the external interface input DBGEN is LOW, this bit reads as 0. The programmed value is masked until DBGEN is HIGH, and at that time the read value reverts to the programmed value.

[13]

ARM

Execute ARM instruction enable bit:

0 = disabled, this is the reset value

1 = enabled.

If this bit is set and an DBGITR write succeeds, the processor fetches an instruction from the DBGITR for execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is Unpredictable.

[12]

Comms

CP14 debug user access disable control bit:

0 = CP14 debug user access enable, this is the reset value

1 = CP14 debug user access disable.

If this bit is set and a User mode process attempts to access any CP14 debug registers, an Undefined Instruction exception is taken.

[11]

IntDis

Interrupts disable bit:

0 = interrupts enabled, this is the reset value

1 = interrupts disabled.

If this bit is set, the IRQ and FIQ input signals are inhibited. The external debugger can optionally use this bit to execute pieces of code in normal state as part of the debugging process to avoid having an interrupt taking control of the program flow. For example, the debugger might use this bit to execute an OS service routine to bring a page from disk into memory. It might be undesirable to service any interrupt during the routine execution.

[10]

DbgAck

DbgAck bit. If this bit is set to 1, the DBGACK output signal is forced HIGH, regardless of the processor state. The external debugger can optionally use this bit to execute pieces of code in normal state as part of the debugging process for the system to behave as if the processor is in debug state. Some systems rely on DBGACK to determine whether data accesses are application or debugger generated. This bit is 0 on reset.

[9]

-

RAZ on reads, SBZP on writes.

[8]

Sticky Undefined

Sticky Undefined bit:

0 = no Undefined Instruction exception occurred in debug state since the last time this bit was cleared

1 = an Undefined Instruction exception occurred while in debug state since the last time this bit was cleared.

This flag detects Undefined Instruction exceptions generated by instructions issued to the processor through the DBGITR. This bit is set to 1 when an Undefined Instruction exception occurs while the processor is in debug state and is cleared by writing a 1 to DBGDRCR[2].

[7]

Sticky asynchronous abort

Sticky asynchronous Data Abort bit:

0 = no asynchronous Data Aborts occurred since the last time this bit was cleared

1 = an asynchronous Data Abort occurred since the last time this bit was cleared.

This flag detects asynchronous Data Aborts triggered by instructions issued to the processor through the DBGITR. This bit is set to 1 when an asynchronous Data Abort occurs while the processor is in debug state and is cleared by writing a 1 to DBGDRCR[2].

[6]

Sticky synchronous abort

Sticky synchronous Data Abort bit:

0 = no synchronous Data Abort occurred since the last time this bit was cleared

1 = a synchronous Data Abort occurred since the last time this bit was cleared.

This flag detects synchronous Data Aborts generated by instructions issued to the processor through the DBGITR. This bit is set to 1 when a synchronous Data Abort occurs while the processor is in debug state and is cleared by writing to the DBGDRCR[2].

[5:2]

MOE

Method of entry bits:

b0000 = a DBGDRCR[0] halting debug event occurred

b0001 = a breakpoint occurred

b0100 = an EDBGRQ halting debug event occurred

b0011 = a BKPT instruction occurred

b1010 = a synchronous watchpoint occurred

others = reserved.

These bits are set to indicate any of:

  • the cause of a debug exception

  • the cause for entering debug state.

A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status Register to determine whether a debug exception occurred and then use these bits to determine the specific debug event.

[1][a]

Core restarted

Core restarted bit:

0 = the processor is exiting debug state

1 = the processor has exited debug state. This is the reset value.

The debugger can poll this bit to determine when the processor responds to a request to leave debug state.

[0][a]

Core halted

Core halted bit:

0 = the processor is in normal state. This is the reset value.

1 = the processor is in debug state.

The debugger can poll this bit to determine when the processor has entered debug state.

[a] These bits always reflect the status of the processor, therefore they only have a reset value if the particular reset event affects the processor. For example, a PRESETDBGn event leaves these bits unchanged and a processor reset event such as nSYSPORESET sets DBGDSCR[18] to a 0 and DBGDSCR[1:0] to 10.


To use the Debug Status and Control Register, read or write CP14 c1 with:

MRC p14, 0, <Rd>, c0, c1, 0 ; Read Debug Status and Control Register
MCR p14, 0, <Rd>, c0, c1, 0 ; Write Debug Status and Control Register

DTR access mode

You can use the DTR access mode field to optimize data transfer between a debugger and the processor.

The DTR access mode can be one of the following:

  • Non-blocking. This is the default mode.

  • Stall.

  • Fast.

In Non-blocking mode, reads from DBGDTRTX and writes to DBGDTRRX and DBGITR are ignored if the appropriate latched ready flag is not in the ready state. These latched flags are updated on DBGDSCR reads. The following applies:

  • writes to DBGDTRRX are ignored if DTRRXfull_l is set to b1

  • reads from DBGDTRTX are ignored, and return an Unpredictable value, if DTRTXfull_l is set to b0

  • writes to DBGITR are ignored if InstrCompl_l is set to b0

  • following a successful write to DBGDTRRX, DTRRXfull and DTRRXfull_l are set to b1

  • following a successful read from DBGDTRTX, DTRTXfull and DTRTXfull_l are cleared to b0

  • following a successful write to DBGITR, InstrCompl and InstrCompl_l are cleared to b0.

Debuggers accessing these registers must first read DBGDSCR. This has the side-effect of copying DTRRXfull and DTRTXfull to DTRRXfull_l and DTRTXfull_l. The debugger must then:

  • write to the DBGDTRRX if the DTRRXfull flag was b0 (DTRRXfull_l is b0)

  • read from the DBGDTRTX if the DTRTXfull flag was b1 (DTRTXfull_l is b1)

  • write to the DBGITR if the InstrCompl_l flag was b1.

However, debuggers can issue both actions together and later determine from the read DBGDSCR value whether the operations were successful.

In Stall mode, the APB accesses to DBGDTRRX, DBGDTRTX, and DBGITR stall under the following conditions:

  • writes to DBGDTRRX are stalled until DTRRXfull is cleared

  • writes to DBGITR are stalled until InstrCompl is set

  • reads from DBGDTRTX are stalled until DTRTXfull is set.

Fast mode is similar to Stall mode except that in Fast mode, the processor fetches an instruction from the DBGITR when a DBGDTRRX write or DBGDTRTX read succeeds. In Stall mode and Nonblocking mode, the processor fetches an instruction from the DBGITR when an DBGITR write succeeds.

Copyright © 2006-2011 ARM Limited. All rights reserved.ARM DDI 0363G
Non-ConfidentialID041111