12.8.10. Exceptions in debug state

While in debug state, exceptions are handled as follows:

Reset

This exception is taken as in a normal processor state. This means the processor leaves debug state because of the system reset.

Prefetch Abort

This exception cannot occur because the processor does not fetch any instructions while in debug state.

Debug

The processor ignores debug events, including BKPT instructions.

SVC

The processor ignores SVC exceptions.

Undefined

When an Undefined Instruction exception occurs in debug state, the behavior of the processor is as follows:

  • PC, CPSR, SPSR_und, and R14_und are unchanged

  • the processor remains in debug state

  • DBGDSCR[8], sticky Undefined bit, is set.

Synchronous Data abort

When a synchronous Data Abort occurs in debug state, the behavior of the processor is as follows:

  • PC, CPSR, SPSR_abt, and R14_abt are unchanged

  • the processor remains in debug state

  • DBGDSCR[6], sticky synchronous data abort bit, is set

  • DFSR and DFAR are set to the same values as if the abort had occurred in normal state.

Asynchronous Data Abort

When an asynchronous Data Abort occurs in debug state, the behavior of the processor is as follows, regardless of the setting of the CPSR A bit:

  • PC, CPSR, SPSR_abt, and R14_abt are unchanged

  • the processor remains in debug state

  • DBGDSCR[7], sticky asynchronous data abort bit, is set

  • the asynchronous Data Abort does not cause the processor to perform an exception entry sequence so DFSR remains unchanged

  • the processor does not act on this asynchronous Data Abort on exit from the debug state, that is, the asynchronous abort is discarded.

Asynchronous Data Aborts on entry and exit from debug state

On entering debug state, the processor executes a Data Synchronization Barrier (DSB) sequence to ensure that any outstanding asynchronous Data Aborts are detected, before starting debug operations.

If the DSB operation detects an asynchronous Data Abort, the processor records this event and its type as if the CPSR A bit was set. The purpose of latching this event is to ensure that it can be taken on exit from the debug state.

Before forcing the processor to leave debug state, the debugger must execute a DSB sequence to ensure that all debugger-generated asynchronous Data Aborts are detected, and therefore discarded, while still in debug state. After exiting debug state, the processor acts on any previously recorded asynchronous Data Aborts if permitted by the CPSR A bit.

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