Cortex-R4 and Cortex-R4F Technical Reference Manual: 11.3.4. Media and VFP Feature Registers, MVFR0 and MVFR1

The MVFR0 and MVFR1 Register characteristics are:

Purpose

Describes the features supported by the FPU.

Usage constraints

The MVFR0 and MVFR1 Registers:

are read-only registers
are accessible in Privileged modes only.
ARM recommends that any software attempting to determine the presence or absence of double-precision floating point hardware support uses the MVFR1 register.

Configurations

Use this register if the device is configured as a Cortex-R4F processor.

Attributes

See Table 11.6 and Table 11.7.

Figure 11.5 shows the MVFR0 Register bit assignments.

Figure 11.5. MVFR0 Register bit assignments

Table 11.6 shows the MVFR0 Register bit assignments.

Table 11.6. MVFR0 Register bit assignments

Bits	Name	Function
[31:28]	RM	All VFP rounding modes supported: `0x1`
[27:24]	SV	VFP short vector unsupported: `0x0`
[23:20]	SR	VFP hardware square root supported: `0x1`
[19:16]	D	VFP hardware divide supported: `0x1`
[15:12]	TE	Only untrapped exception handling can be selected: `0x0`
[11:8]	DP	Double precision supported in VFPv3: `0x2`
[7:4]	SP	Single precision supported in VFPv3: `0x2`
[3:0]	RB	16x64-bit media register bank supported: `0x1`

Figure 11.6 shows the MVFR1 Register bit assignments.

Figure 11.6. MVFR1 Register bit assignments

Table 11.7 shows the MVFR1 Register bit assignments.

Table 11.7. MVFR1 Register bit assignments

Bits	Name	Function
[31:20]	-	Reserved
[19:16]	SP	Single-precision floating-point operations supported for VFP: `0b0000` = not supported
[15:12]	I	Integer operations supported for VFP: `0b0000` = not supported
[11:8]	LS	Load and store instructions supported for VFP: `0b0000` = not supported
[7:4]	DN	Propagation of NaN values supported for VFP: `0x1`
[3:0]	FZ	Full denormal arithmetic supported for VFP: `0x1`

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