A.9. ETM interface signals

Table A.14 shows the ETM interface signals.

Table A.14. ETM interface signals

SignalDirectionClockingDescription
ETMICTL[13:0]OutputCLKINETM instruction control bus
ETMIA[31:1]OutputCLKINETM instruction address
ETMDCTL[11:0]OutputCLKINETM data control bus
ETMDA[31:0]OutputCLKINETM data address
ETMDD[63:0]OutputCLKINETM data-data
ETMCID[31:0]OutputCLKINValue of processor CID register
ETMWFIPENDINGOutputCLKINCore is attempting to enter WFI state
EVNTBUS[46:0]OutputCLKINPerformance monitor unit output
ETMPWRUPInputCLKINPower up ETM interface
nETMWFIREADYInputCLKINETM FIFO is empty, core can enter WFI state
ETMEXTOUT[1:0]InputCLKINETM detected events

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