A.10. Test signals

Table A.15 shows the test signals.

Table A.15. Test signals

SignalDirectionClockingDescription
SEInput-[a]Scan Enable
RSTBYPASSInput-[a]Bypass pipelined reset

[a] Design for test only.


Copyright © 2006-2011 ARM Limited. All rights reserved.ARM DDI 0363G
Non-ConfidentialID041111