Cortex-R4 and Cortex-R4F Technical Reference Manual: C.11. Single load and store instructions

C.11. Single load and store instructions

This section describes the cycle timing behavior for LDR, LDRHT, LDRSBT, LDRSHT, LDRT, LDRB, LDRBT, LDRSB, LDRH, LDRSH, STR, STRT, STRB, STRBT, STRH, and PLD instructions.

Table C.12 shows the cycle timing behavior for stores and loads, other than loads to the PC. You can replace LDR with any of these single load or store instructions. The following rules apply:

They are normally single-cycle issue. Both the base and any offset register are Very Early Regs.
They are 3-cycle issue if pre-increment addressing with either a negative register offset or a shift other than LSL #1, 2 or 3 is used. Both the base and any offset register are Very Early Regs.
If unaligned support is enabled then accesses to addresses not aligned to the access size that cross a 64-bit aligned boundary generate two memory accesses, and require an additional cycle to issue. This extra cycle is required if the final address is potentially unaligned, even if the final address turns out to be aligned.
PLD (data preload hint instructions) have cycle timing behavior as for load instructions. Because they have no destination register, the result latency is not-applicable for such instructions.
For store instructions <Rt> is always a Late Reg.

Table C.12. Cycle timing behavior for stores and loads, other than loads to the PC

Example instruction	Cycles	Memory cycles	Result latency (LDR)	Result latency (base register)	Comments
`LDR <Rt>, <addr_md_1cycle>`^[a]	1	1	2	1	Aligned access
`LDR <Rt>, <addr_md_3cycle>`^a	3	1	4	3	Aligned access
`LDR <Rt>, <addr_md_1cycle>`^a	2	2	3	2	Potentially unaligned access
`LDR <Rt>, <addr_md_3cycle>`^a	4	2	5	4	Potentially unaligned access
^[a]See Table C.14 for an explanation of `<addr_md_1cycle>` and `<addr_md_3cycle>`.

Table C.13 shows the cycle timing behavior for loads to the PC.

Table C.13. Cycle timing behavior for loads to the PC

Example instruction	Cycles	Memory cycles	Result latency	Comments
`LDR pc, [sp, #<imm>] (!)`	1	1	-	Correctly return stack predicted, or conditional predicted correctly
`LDR pc, [sp], #<imm>`	1	1	-
`LDR pc, [sp, #<imm>] (!)`	9	1	-	Return stack mispredicted, conditional predicted correctly
`LDR pc, [sp], #<imm>`	9	1	-	Return stack mispredicted, conditional predicted correctly
`LDR <cond> pc, [sp, #<imm>] (!)`	8	1	-	Conditional predicted incorrectly, but return stack predicted correctly
`LDR <cond> pc, [sp], #cn`s	8	1	-
`LDR pc, <addr_md_1cycle>`^[a]	9	1	-	-
`LDR pc, <addr_md_3cycle>^a`	11	1	-	-
^[a]See Table C.14 for an explanation of `<addr_md_1cycle>` and `<addr_md_3cycle>`. For condition code failing cycle counts, you must use the cycles for the non-PC destination variants.

Only cycle times for aligned accesses are given because Unaligned accesses to the PC are not supported.

The processor includes a 4-entry return stack that can predict procedure returns. Any LDR instruction to the PC with an immediate post-indexed offset of plus four, and the stack pointer R13 as the base register is considered a procedure return.

Table C.14 shows the explanation of <addr_md_1cycle> and <addr_md_3cycle> used in Table C.12 and Table C.13.

Table C.14. <addr_md_1cycle> and <addr_md_3cycle> LDR example instruction explanation

Example instruction		Very Early Reg	Comments
`<addr_md_1cycle>`
	`LDR <Rt>, [<Rn>, #<imm>] (!)`	`<Rn>`	If post-increment addressing or pre-increment addressing with an immediate offset, or a positive register offset with no shift or shift LSL #1, 2 or 3, then 1-issue cycle
	`LDR <Rt>, [<Rn>, <Rm>] (!)`	`<Rn>, <Rm>`
	`LDR <Rt>, [<Rn>, <Rm>, LSL #1, 2 or 3] (!)`	`<Rn>, <Rm>`
	`LDR <Rt>, [<Rn>], #<imm>`	`<Rn>`
	`LDR <Rt>, [<Rn>], +/-<Rm>`	`<Rn>, <Rm>`
	`LDR <Rt>, [<Rn>], +/-<Rm> <shift> <cns>`	`<Rn>, <Rm>`
`<addr_md_3cycle>`
	`LDR <Rt>, [<Rn>, -<Rm>] (!)`	`<Rn>,<Rm>`	If pre-increment addressing with a negative register offset or shift other than LSL #1, 2 or 3, then 3-issue cycles
	`LDR <Rt>, [Rn, +/-<Rm> <shift> <cns>] (!)`	`<Rn>,<Rm>`

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