A.3. Configuration signals

Table A.2 shows the processor configuration signals.

Table A.2. Configuration signals

SignalDirectionClockingDescription
VINITHIInputTie-off, ResetReset V-bit value. When HIGH indicates HIVECS mode at reset. See c1, System Control Register for more information.
CFGEEInputTie-off, ResetReset EE-bit value. When HIGH indicates the implementation uses BE-8 mode for exceptions at reset. See c1, System Control Register for more information.
CFGIEInputTie-off, ResetInstruction side endianness, reflected in the IE-bit. When HIGH indicates that big endian instruction fetch is used. See c1, System Control Register for more information.
INITRAMAInputTie-off, ResetReset value of ATCM enable bit. When HIGH indicates Tightly-Coupled Memory A, ATCM, enabled at reset. See c9, ATCM Region Register for more information.
INITRAMBInputTie-off, ResetReset value of BTCM bit. When HIGH indicates Tightly-Coupled Memory B, BTCM, enabled at reset. See c9, BTCM Region Register for more information.
LOCZRAMAInputTie-off, Reset

When HIGH indicates ATCM initial base address is zero and BTCM base address is implementation-defined.

When LOW indicates BTCM initial base address is zero and ATCM base address is implementation-defined.

TEINITInputTie-off, Reset

Reset TE-bit value. Determines exception handling state at reset. When set to:

0 = ARM

1 = Thumb.

See c1, System Control Register for more information.

CFGATCMSZ[3:0]InputTie-off

Selects the ATCM size. The encodings for the TCM sizes are:

b0000 = 0KB

b0011 = 4KB

b0100 = 8KB

b0101 = 16KB

b0110 = 32KB

b0111 = 64KB

b1000 = 128KB

b1001 = 256KB

b1010 = 512KB

b1011 = 1MB

b1100 = 2MB

b1101 = 4MB

b1110 = 8MB.

CFGBTCMSZ[3:0]InputTie-off

Selects the BTCM size. The encodings for the TCM sizes are:

b0000 = 0KB

b0011 = 4KB

b0100 = 8KB

b0101 = 16KB

b0110 = 32KB

b0111 = 64KB

b1000 = 128KB

b1001 = 256KB

b1010 = 512KB

b1011 = 1MB

b1100 = 2MB

b1101 = 4MB

b1110 = 8MB.

CFGNMFIInputTie-off, ResetWhen HIGH, enable non-maskable Fast Interrupts. Reflected in the NMFI bit. See c1, System Control Register for more information.
ENTCM1IFInputTie-off

Enable B1TCM interface.

Use B0TCM only if this signal not tied HIGH.

PARECCENRAM[2:0]InputTie-off, Reset

TCMs parity or ECC check enable. Tie each bit HIGH to enable parity or ECC checking on the appropriate TCM at reset. Use following values:

[2]:B1TCM[a]

[1]: B0TCMa

[0]: ATCM

See c1, Auxiliary Control Register for more information.

PARLVRAMInputTie-off, Reset

Selects between odd and even parity for caches, TCMs, and buses. See Chapter 8 Level One Memory System:

Tie LOW for even parity

Tie HIGH for odd parity.

ERRENRAM[2:0]InputTie-off, Reset

TCMs external error enable. Tie each bit high to enable the external error signals for each TCM at reset. Use the following values:

[2]: B1TCM

[1]: B0TCM

[0]: ATCM

See c1, Auxiliary Control Register for more information.

RMWENRAM[1:0][b]InputTie-off, Reset

RMW enable bits reset values. Tie each bit high to enable read-modify-write for TCM interfaces at reset.[c] Use the following values:

[1]: BTCM

[0]: ATCM

See c1, Auxiliary Control Register for more information.

SLBTCMSBInputTie-off

Use most significant bit of BTCM address to select B1TCM if this signal is HIGH.

Use bit [3] of the BTCM address if this signal is LOW.

[a] If the BTCM is configured with ECC, bit[2] and bit[1] must be the same value.

[b] Not used if 32-bit ECC is included.

[c] Not available in r0px revisions of the processor.


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