A.8. Debug interface signals

Table A.12 shows the debug interface signals. With the exception of PCLKDBG, PCLKENDBG and PRESETDBGn, all these signals are only sampled or driven on PCLKDBG edges when PCLKENDBG is asserted.

Table A.12. Debug interface signals

SignalDirectionClockingDescription
PCLKDBGInput-Debug clock.
PCLKENDBGInputPCLKDBGClock enable for PCLKDBG.
PSELDBGInputPCLKDBGSelects the external debug interface.
PADDRDBG[11:2]InputPCLKDBGProgramming address.
PADDRDBG31InputPCLKDBGProgramming address.
PRDATADBG[31:0]OutputPCLKDBGRead data bus.
PWDATADBG[31:0]InputPCLKDBGWrite data bus.
PENABLEDBGInputPCLKDBGIndicates second, and subsequent, cycle of a transfer.
PREADYDBGOutputPCLKDBGExtends a APB transfer by the inserting wait states.
PSLVERRDBGOutputPCLKDBGSlave-generated error response.
PWRITEDBGInputPCLKDBG

Indicates access is a write transfer.

Distinguishes between a read, LOW, and a write, HIGH.

PRESETDBGnInputAnyReset debug logic.

Table A.13 shows the debug miscellaneous signals.

Table A.13. Debug miscellaneous signals

NameDirectionClockingDescription
DBGENInputAnyDebug enable
NIDENInputAnyNon-invasive debug enable
EDBGRQInput

Any

External debug request
DBGACKOutputCLKINDebug acknowledge
DBGRSTREQ[a]OutputPCLKDBGRequest for reset from debug logic
DBGTRIGGEROutputCLKINExternal debug request taken
COMMRXOutputCLKINDBGDTRRX full
COMMTXOutputCLKINDBGDTRTX empty
DBGRESTARTInput External restart request
DBGRESTARTEDOutputCLKINHandshake for DBGRESTART
DBGNOPWRDWNOutputPCLKDBGNo power-down request
DBGROMADDR[31:12]InputTie-offDebug ROM physical address
DBGROMADDRVInputTie-offDebug ROM physical address valid
DBGSELFADDR[31:12]InputTie-offDebug self-address offset
DBGSELFADDRVInputTie-offDebug self-address offset valid

[a] Not available in r0px revisions of the processor.


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