4.3.1. Register allocation

Table 4.2 shows a summary of address allocation and reset values for the registers in the system control coprocessor where:

Table 4.2. Summary of CP15 registers and operations

CRnOp1CRmOp2Register or operationTypeReset valuePage
c00c0{0, 3, 6-7}Main ID Read-only0x41xFC14x[a]c0, Main ID Register
  1Cache TypeRead-only0x8003C003c0, Cache Type Register
  2TCM TypeRead-only0x00010001c0, TCM Type Register
  4MPU TypeRead-only-[b]c0, MPU Type Register
  5Multiprocessor AffinityRead-only-[d]c0, Multiprocessor ID Register
 c10Processor Feature 0Read-only0x00000131c0, Processor Feature Register 0
  1Processor Feature 1Read-only0x00000001c0, Processor Feature Register 1
  2Debug Feature 0Read-only0x00010400c0, Debug Feature Register 0
  3Auxiliary Feature 0Read-only0x00000000c0, Auxiliary Feature Register 0
  4Memory Model Feature 0Read-only0x00210030c0, Memory Model Feature Register 0
  5Memory Model Feature 1Read-only0x00000000c0, Memory Model Feature Register 1
  6Memory Model Feature 2Read-only0x01200000c0, Memory Model Feature Register 2
  7Memory Model Feature 3Read-only0x00000211c0, Memory Model Feature Register 3
 c20Instruction Set Attributes 0Read-only0x01101111c0, Instruction Set Attributes Register 0
c00c21Instruction Set Attributes 1Read-only0x13112111c0, Instruction Set Attributes Register 1
   2Instruction Set Attributes 2Read-only0x21232131c0, Instruction Set Attributes Register 2
   3Instruction Set Attributes 3Read-only0x01112131c0, Instruction Set Attributes Register 3
   4Instruction Set Attributes 4Read-only0x00010142c0, Instruction Set Attributes Register 4
   5Instruction Set Attributes 5Read-only0x00000000c0, Instruction Set Attributes Register 5
   6-7Reserved, Read As Zero (RAZ)Read-only0x00000000c0, Instruction Set Attributes Register 5
  c3-c70-7Reserved, RAZRead-only0x00000000-
  c8-c150-7Undefined---
 1c00Current Cache Size ID Read-only-[c][d]c0, Current Cache Size Identification Register
   1Current Cache Level IDRead-only-[c]c0, Current Cache Level ID Register
   2-7Undefined---
  c1-c150-7Undefined---
 2c00Cache Size SelectionRead/writeUnpredictablec0, Cache Size Selection Register
c10c00System ControlRead/write-[d]c1, System Control Register
   1Auxiliary ControlRead/write-[d]c1, Auxiliary Control Register
   2Coprocessor Access

Read/write

0x00000000c1, Coprocessor Access Register
   3-7Undefined---
  c1-c150-7    
c2-c40c0-c150-7    
c50c00Data Fault StatusRead/write

Unpredictable

c5, Data Fault Status Register
   1Instruction Fault StatusRead/write

Unpredictable

c5, Instruction Fault Status Register
   2-7Undefined---
  c10Auxiliary Data Fault StatusRead/write

Unpredictable

c5, Auxiliary Fault Status Registers
c50c11Auxiliary Instruction Fault StatusRead/write

Unpredictable

c5, Auxiliary Fault Status Registers
  2-7Undefined---
  c2-c150-7    
c60c00Data Fault AddressRead/write

Unpredictable

c6, Data Fault Address Register
   1Undefined---
   2Instruction Fault AddressRead/write

Unpredictable

c6, Instruction Fault Address Register
   3-7Undefined---
  c10MPU Region Base AddressRead/write0x00000000c6, MPU Region Base Address Registers
   1Undefined---
   2MPU Region Size and EnableRead/write0x00000000c6, MPU Region Size and Enable Registers
   3Undefined---
   4MPU Region Access ControlRead/write0x00000000c6, MPU Region Access Control Registers
   5-7Undefined---
  c20MPU Memory Region NumberRead/write0x00000000c6, MPU Memory Region Number Register
   1-7Undefined---
  c3-c151-7    
c70c00-3Undefined---
   4NOP, previously Wait For InterruptWrite-only-Cache operations
   5-7Undefined---
  c1-c40-7    
  c50Invalidate entire instruction cacheWrite-only-Invalidate and clean operations
c70c51Invalidate instruction cache line by address to Point-of-Unification.Write-only-Invalidate and clean operations
2-3Undefined---
4Flush prefetch bufferWrite-only-Invalidate and clean operations
5Undefined---
6Invalidate entire branch predictor arrayWrite-only-Invalidate and clean operations
   7Invalidate address from branch predictor arrayWrite-only-Invalidate and clean operations
  c60Undefined---
   1Invalidate data cache line by physical addressWrite-only-Invalidate and clean operations
   2Invalidate data cache line by Set/WayWrite-only-Invalidate and clean operations
   3-7Undefined---
  c7-90-7    
  c100    
   1Clean data cache line by physical addressWrite-only-Invalidate and clean operations
   2Clean data cache line by Set/WayWrite-only-Invalidate and clean operations
   3Undefined---
   4Data Synchronization BarrierWrite-only-Data Synchronization Barrier operation
   5Data Memory BarrierWrite-only-Data Memory Barrier operation
   6-7Undefined---
  c110    
c70c111Clean data cache line by physical address to Point-of-UnificationWrite-only-Invalidate and clean operations
 2-7Undefined---
c12-c130-7    
c140    
 1Clean and invalidate data cache line by physical address to Point-of-UnificationWrite-only-Invalidate and clean operations
c142Clean and invalidate data cache line by Set/WayWrite-only-Invalidate and clean operations
  3-7Undefined---
  c150-7    
c80c0-c150-7Undefined---
c90c00-7Undefined---
  c10BTCM RegionRead/write

-[d]

c9, BTCM Region Register
   1ATCM Region Read/write-[d]c9, BTCM Region Register
   2-7Undefined---
  c20TCM selectionRead/write0x00000000c9, TCM Selection Register
   1-7Undefined---
  c3-c110-7    
  c120Performance Monitor ControlRead/write0x41141800c9, Performance Monitor Control Register
   1Count Enable Set Read/write

Unpredictable

c9, Count Enable Set Register
   2Count Enable Clear Read/writeUnpredictablec9, Count Enable Clear Register
   3Overflow Flag Status Read/writeUnpredictablec9, Overflow Flag Status Register
   4Software Increment Write-only-c9, Software Increment Register
c90c125Performance Counter Selection Read/writeUnpredictablec9, Performance Counter Selection Register
   6-7Undefined---
  c130Cycle Count Read/write0x00000000c9, Cycle Count Register
   1Event Select Read/writeUnpredictablec9, Event Type Selection Register
   2Performance Monitor CountRead/write0x00000000c9, Event Count Registers
   3-7Undefined---
  c140User Enable Read/write0x00000000c9, User Enable Register
 1Interrupt Enable Set Read/writeUnpredictablec9, Interrupt Enable Set Register
c142Interrupt Enable Clear Read/writeUnpredictablec9, Interrupt Enable Clear Register
 3-7Undefined---
  c150-7    
c100c0-c150-7Undefined---
c110c00Slave Port ControlRead/write0x00000000c11, Slave Port Control Register
  c01-7Undefined---
  c1-c150-7    
c120c0-c150-7    
c130c00FCSE PID

RAZ, ignore writes

0x00000000c13, FCSE PID Register
   1Context IDRead/write0x00000000c13, Context ID Register
   2User read/write Thread and Process IDRead/write
0x00000000
c13, Thread and Process ID Registers
   3User Read-only Thread and Process IDRead/write
0x00000000
c13, Thread and Process ID Registers
   4Privileged Only Thread and Process IDRead/write
0x00000000
c13, Thread and Process ID Registers
   5-7Undefined---
c130c1-c150-7Undefined---
c140c0-c150-7    
c150c00Secondary Auxiliary ControlRead/write-[d]c15, Secondary Auxiliary Control Register
 1-7Undefined---
c10nVAL IRQ Enable SetRead/writeUnpredictablec15, nVAL IRQ Enable Set Register
 1nVAL FIQ Enable SetRead/writeUnpredictablec15, nVAL FIQ Enable Set Register
 2nVAL Reset Enable SetRead/writeUnpredictablec15, nVAL Reset Enable Set Register
 3nVAL Debug Request Enable SetRead/writeUnpredictablec15, VAL Debug Request Enable Set Register
 4nVAL IRQ Enable ClearRead/writeUnpredictablec15, nVAL IRQ Enable Clear Register
c15nVAL FIQ Enable ClearRead/writeUnpredictablec15, nVAL FIQ Enable Clear Register
   6nVAL Reset Enable ClearRead/writeUnpredictablec15, nVAL Reset Enable Clear Register
   7nVAL Debug Request Enable ClearRead/writeUnpredictablec15, VAL Debug Request Enable Clear Register
  c20Build Options 1Read-only-[d]c15, Build Options 1 Register
   1Build Options 2Read-only-[d]c15, Build Options 2 Register
   2-7Undefined---
  c30Correctable Fault LocationRead/writeUnpredictableCorrectable Fault Location Register
   1-7Undefined---
  c40-7    
  c50Invalidate all data cacheWrite-only-Invalidate and clean operations
   1-7Undefined---
  c6-c130-7    
c150c140Cache Size OverrideWrite-only-c15, Cache Size Override Register
   1-7Undefined---
  c150-7    

[a] The value of bits [23:20,3:0] of the MIDR depend on product revision. See the register description for more information.

[b] Reset value depends on number of MPU regions.

[c] Reset value depends on which caches are implemented, and their sizes.

[d] See register description for more information.


Copyright © 2006-2011 ARM Limited. All rights reserved.ARM DDI 0363G
Non-ConfidentialID041111