1.2. PTB overview

The PTB is part of a methodology for creating a standard test interface for all peripherals within a SoC. It enables the re-use of the block between different validation environments and gives a generic register structure for the verification/validation engineer. The block sits between the peripheral I/O signals, Direct Memory Access (DMA) interface, interrupt request signals and the validation environment.

The PTB is placed in the validation environment as shown in Figure 1.1.

Figure 1.1. PTB integration overview

If the environment contains the Direct Memory Access Controller (DMAC) and Interrupt Controller (IC) then the PTB can act as a pass through for these signals and perform a monitoring only function. If these components are not present then the PTB can generate events on these signals, enabling emulation of the IC and DMAC for validating these interfaces on the PrimeCell.

The Peripheral Test Interface Bus (PTIB) contained within the Peripheral Test Wrapper (PTW) enables a common interface using the AMBA APB 2.0 interface specification to either:

The PTB has an address space of 4KB in the basic register level interface. Using the PTIB it occupies 4 words of memory space. This is useful if address space is an issue, especially in static memory mapped implementations.

The SMC asynchronous memory interface is mainly for platform level validation. It enables the PTB to be placed externally to the platform.

Copyright © 2005 ARM Limited. All rights reserved.ARM DDI 0364A