1.3.3. Platform

The PTB is designed to operate in this environment to prove the functionality of the PrimeCell at a system level using a real processor and system level components.

It is desirable for the PTB to provide loop-back functionality to assist with in-system testing. This enables testing to be performed without having to access the control interface on the PTB, and is more representative of real operation of the peripheral.There can be peripherals where the PTB functionality is replaced by an external peripheral, and autonomous operation of the PTB can mimic this.

Figure 1.5 shows the platform environment.

Figure 1.5. Platform environment

In a system environment, it is necessary to instantiate the PTB external to the system being tested. In this environment, there might be no means for direct connection from the processor running tests and the PTB. Therefore, you must re-use an existing interface on the system to provide control of the PTB.

By using the Static Memory Controller (SMC) as the interface through the PTW to the PTB, you can perform system level testing without modifications to the internal structure of the SoC platform. The SMC is the interface to the PTB for all data transfers. You can map the PTB externally by additional decode logic that can sit in unused SMC memory area. This interface models simple asynchronous SRAM.

The small memory footprint of the PTB interface is aimed specifically at this platform requirement, because many PTBs can sit in a single SMC area above the normal SRAM memory.

Any events generated by the PTB are signalled through the external interrupt input of the platform. If an external interrupt is not available then you can use the platform General Purpose Input/Output (GPIO) with the input pin configured to raise an interrupt on the event signal.

The peripheral DMA and interrupt signals are wired in the system, so if you require the PTB, use it in a monitoring only mode.

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