2.2.7. FIFO options for usage models

The width and depth of the FIFO is not fixed in the PTB. It can have any width from 1 to 2048 bits and any depth as long as it is a power of two. The choice of width and depth is application specific, however in general the width is defined by the amount of data required at the peripheral interface in a single clock cycle.

This section describes:

FIFO width

Because the accesses to the FIFO are limited to 32 bit words then it takes the same amount of time at the PTI to read or write a bit wide, byte wide or word wide FIFO. Therefore for optimum performance at the PTI interface a FIFO width of less than a word is in efficient and must only be used for very low data rate applications, but ideally not used at all.

FIFOs larger than a word have the same level of performance as a word wide FIFO, because the number of accesses to write the data is related to the number of word writes at the PTI. For example, a 66 bit wide packet with a 66 bit wide FIFO requires three word accesses for a packet transfer because the PTI interface is 32 bits wide. If the FIFO were 32 bits wide then it still requires three accesses to transfer the packet. The width of the FIFO in this case is determined by the rate the data requirements reading at the PI.

It is sometimes best for synchronization and tracing to keep the FIFO width equal to the packet width and enable the depth to determine the level of buffering required.

Continuous data streams

For a continuous data stream application, for example Color Liquid Crystal Display (CLCD), the latency in responding to a request to fill/empty the FIFO defines the depth of the FIFO. You must assume that the FIFO can be filled/emptied faster than it can be emptied/filled at the peripheral end.

High data rate burst streams

Because some applications have a large block of data with a high burst transfer rate, that is greater than the ability to fill/empty the FIFO from the PTI, but a low average data rate, then it would be beneficial for the size of the FIFO to match the size of the data packet. You can define the depth of the FIFO by the data packet size divided by the width of the FIFO. The minimum width is defined as the amount of data required at the PI interface in a single clock cycle.

Example FIFO configurations

If you require an application that supplies six packets of data with a data rate of 120 bits per clock cycle, then Figure 2.9 shows a typical example that holds six data packets in the FIFO.

Figure 2.9. Example FIFO configuration 1

If the data rate is halved to 60 bits per clock cycle then the width of the FIFO can be reduced and the depth increased, with the packet spread across two FIFO registers, as shown in Figure 2.10.

Figure 2.10. Example FIFO configuration 2

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