2.2.2. Transferring data between clock domains

This section consists of:

Note

To synchronize multiple control and status accesses, they are gated by writes to the Xfer Register. The same register is used to check that the information has been passed from one clock domain to the next.

Control, from PTI to PI

You can access the control registers as 32 bit wide registers from the PTI. You can write to any of these registers in any order. The contents of all the 32 bit wide control registers are transferred in a single cycle onto the control bus when the Xfer Register commit bit is set. Polling the commit bit for a 1 indicates when the transfer from the PTI to PI has completed and the PI has the new values in its registers.

Status, from PI to PTI

You can access the status registers as 32 bit wide registers from the PTI. You can read any of these registers in any order. The contents of all the 32 bit wide status registers are loaded in a single cycle from the status bus when the Xfer Register sample bit is set. Polling the sample bit for a 1 indicates when the transfer from PI to PTI has completed and registers have valid data.

Events, from PI to PTI

The event signals are re-synchronized into the PTI clock domain by double buffering logic. Each event is a single signal so no specific requirement is placed on making sure some signals do not change before others.

If you require transfers of information that are greater than a single bit, then place the information on the status bus and generate an event signal to indicate that information is available. When the event is processed the PTI can read the status bus, defined in Status, from PI to PTI to recover the required information.

Read buffer, from PI to PTI

The read buffer is able to support asynchronous transfers between the two clock domains, as either a dual ported RAM or FIFO.

In a FIFO implementation the status of the RdFifoEmpty flag indicates if data is ready for reading. You can use the RdFifoTide flag to indicate that a burst transfer of reads can occur. The tide level is set to the number of words before the FIFO is empty.

In a Dual Ported RAM (DPRAM) implementation it is the responsibility of the PTI to ensure that the data written is not going to overwrite the reading location. You can achieve this by stopping the PI from writing to the DPRAM when the PTI wants to read the data, although this could cause issues for streaming data. Alternatively, you can split the DPRAM into multiple blocks and generate an event when a block is filled. This procedure enables the PTI to read this block by monitoring the RdFifoTide flag, while the PI moves onto filling the next block. By reading the RdBufPIAddr Register, it is possible to see which block is being filled. The RdBufPTIAddr Register holds the present reading location, and therefore the reading block. From this, if an event has been missed, it is possible to determine by how many blocks the reading is lagging the writing. The RdBufControl Register bits RdBlockSize set the size of the block in words to generate the RdFifoTide flag event when that size is crossed. This size is a power of 2 and can be up to 64K Words.

Write buffer, from PTI to PI

The write buffer is able to support asynchronous transfers between the two clock domains as either a dual ported RAM or FIFO. In a FIFO implementation the status of the WrFifoFull flag indicates if space is available for writing. The WrFifoTide flag can be used to indicate that a burst transfer of data can occur. Here the tide level is set to the number of words before the FIFO is full.

In a Dual Ported RAM (DPRAM) implementation, it is the responsibility of the PTI to ensure that the data written is not going to overwrite the reading location. You can achieve this by stopping the PI from reading from the DPRAM when the PTI wants to write the data, although this could cause issues for streaming data. Alternatively, you can split the DPRAM into multiple blocks and generate an event when a block is fully read. This procedure enables the PTI to write to this block again by monitoring the WrFifoTide flag. By reading the WrBufPIAddr Register it is possible to see which block is being read. The WrBufPTIAddr Register holds the present writing location and therefore the writing block. From this, if an event has been missed, it is possible to determine by how many blocks the writing is leading the reading. The WrBufControl Register bits WrBlockSize set the size of the block in words. The PTI logic generates the WrFifoTide flag event when this size is crossed. This size is a power of two, and can be up to 64K Words.

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