2.2.1. PTB internal structure

Figure 2.2 shows the PTB internal structure.

Figure 2.2. PTB internal structure

The PTB consists of four elements:

This section describes:

Peripheral interface logic (PI)

The PI logic works in the peripheral clock domain and performs data translation for the transfer of data at the peripheral specific interface. Protocol checking of this data and associated signals are performed by formal methods and HDL behavior. It also controls the transfer of data for the buffers.

Buffers

The buffers can be implemented as a FIFO or a dual ported RAM depending on the peripheral requirements. Each buffer is up to 8K bits wide, split into 32 bit registers, and the two interfaces of each buffer, to the PI or PTI, are in their respective clock domain.

The PTI interface has the ability to monitor the buffer status and reset the FIFO levels, or set the dual ported RAM address pointers.

When a dual ported RAM receive buffer implementation is used, you are required to select the option of filling the RAM with an image from the PTI. By setting the PI receive mode to compare, the image in the RAM is compared with the incoming data and an event is raised if a mismatch occurs or when the image has been read completely.

If you require buffers wider than 32 bits, then the most significant register is used to transfer the data into or alternatively to read the next value from the FIFO. For an example, a procedure for a read operation to a 96 bit register would be:

  1. Read least significant register first then read incrementing registers to build up the data. The last register signals that the FIFO read is complete and the next FIFO value is ready for reading.

  2. Write least significant register up to most significant register.

    Note

    The write to the most significant register transfers data from the holding registers into the FIFO/RAM.

Peripheral test interface logic

The PTI logic interfaces with the Register Level Interface APB bus to the internal registers enabling access to the buffers, control and status buses as word wide registers. It re-synchronizes signals from the PI logic, that is, the status and event signals.

Internal signals

These consist of:

Status bus

The status signals are outputs from the PI logic to show the internal status of the PI and the signal levels at the peripheral specific interface, for example UART signals DTR, RTS. The signals are generated in the peripheral clock domain and require re-synchronizing to the PTI clock domain. You can determine the width of the status bus by the number of status signals required. The width is peripheral specific, that is, up to 8K bits.

Control bus

The control signals are inputs to the PI logic. Their functionality is defined on a peripheral basis but can include setting of output signals, for example UART signals DSR, CTS. The control signals are in the PTI clock domain and require re-synchronizing to the peripheral clock domain. You can determine the width of the control bus by the number of control signals required. This is peripheral specific, and up to 8K bits.

Event bus

The event signals are outputs from the peripheral PI logic to signal that a condition has occurred requiring immediate attention. The number of events is limited to 32. The signals are generated in the peripheral clock domain and require re-synchronizing to the PTI clock domain.

Copyright © 2005 ARM Limited. All rights reserved.ARM DDI 0364A
Non-Confidential