2.2.6. Peripheral test interface bus

The standard interface to the PTB requires 4K bytes, 1K words, of address space. When multiple PTBs exist in the system this could require an address space larger than available, for example, an external memory interface. In this situation you can use the PTIB to reduce the number of addressable registers to four for each PTB. This enables 256 PTBs to occupy the same address space as a single PTB, of size 4K bytes. This does add a level of indirection to the register accesses. You must handle this by a generic device driver software that can sit between the normal driver and the hardware for the PTB. In normal operation this drive is in pass through mode. In PTIB operation, it performs the address/data translation for the PTIB.

Each PTB occupies four words of memory. The device consists of four registers:

  1. An event register, EVENT. You can read it to indicate if any trigger events have occurred.

  2. An address register, ADDR which is written to select the required memory location for access, or read to determine which memory location is selected.

  3. The non incrementing data register, SINGLE. It is read/write capable to enable access to the specified memory location referenced by ADDR. When you access this register, the ADDR Register is not modified.

  4. The incrementing data register, INCR. It is read/write capable to enable access to the specified memory location referenced by ADDR. After the access the ADDR Register is incremented.

You can use the INCR Register to enable fast access for writing/reading large blocks of memory, such as the DPRAMS.

You can use the ADDR Register to enable the internal structure of the PTB to access the full 4K bytes of the PTB memory space while maintaining a small memory footprint to the outside.

The PTIB is an APB interface with a 32 bit data bus and associated command signals. It has a two cycle response:

The device can perform single transfers or burst transfers to/from the PTB register interface. The registers are single transfer access only. Each PTB occupies four contiguous words of memory. All accesses are 32 bit wide only and unused addresses and bits within decoded addresses must be returned as zero.

PTIB timing

You can access any register within the PTB by writing the address required to offset 0x4, the ADDR Register, and then reading or writing, at offset 0x8 for a non-incrementing access or at 0xC for post incrementing accesses. Reading the ADDR Register gives the address being pointed to for the next data access.

Address 0x00 is a read only register returning the status of the masked events register.

Transfers must assert the PSEL signal active for the required PTB otherwise the transfer is ignored. This structure enables multiple PTBs to be placed alongside one another in a small area of memory, 256 PTBs use 4K of address space, therefore they can sit in a small area of the memory map of the static/dynamic memory controller.

Figure 2.7 shows non-incrementing read/write timing. For a non-incrementing transfer the required register address is first written to offset 0x004 ADDR Register at time t2-t3, data for this register is then read or written at time t4-t5.

Figure 2.7. Non-incrementing read/write timing

Figure 2.8 shows incrementing read/write. For an incrementing transfer the required register address is first written to offset 0x004 ADDR Register, at time t2-t3. At time t4-t5 data for this register is then read or written and the ADDR Register is incremented. This enables a read or write at time t6-t7 to the next adjacent register.

Figure 2.8. Incrementing read/write timing

Table 2.1 lists the PTIB address map.

Table 2.1. PTIB address map

Offset Mode NameDescription
0x0 R EVENT Output of the masked events register.
0x4 R/W ADDR Address of register to access, points to present address to be accessed in incrementing mode.
0x8 R/W SINGLE Single address access, non incrementing.
0xC R/W INCRPost incrementing address access.
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