2.2.3. XVC data transfer

Figure 2.3 shows the XVC data transfer.

Figure 2.3. XVC data transfer

XVC transfers are:

Control, from XVC to PI

The control bus is directly driven from the XVC. The XVC can modify all bits of the control bus in a single access. This means that control signalling is simpler than it is for the PTI interface. Because the signals are all set in zero time, the commit bit is not required in the Xfer Register.

The difference between the PTI and XVC in this situation is that the data is not written in the PTI clock domain, so the XVC must be aware of a time difference between the PTI and XVC values being placed on the control bus.

Status, from PI to XVC

The status bus is directly read by the XVC. It can read the whole bus width in zero time. This removes the requirement to sample the status bus into registers before reading and therefore the sample bit in the Xfer Register is not required.

The difference between the PTI and XVC in this situation is that the data is read in the PI clock domain, the PTI reads data in the PTI clock domain, so the XVC must be aware of a time difference between the PTI and XVC values.

Events, from PI to XVC

The XVC directly monitors these signals. The XVC must use these signals to monitor activity to determine when to perform transfers.

The XVC does not require re-synchronizing of the event signals into the PTI clock domain so the events can been seen at an earlier time compared to the PTI.

Read buffer, from PI to XVC

In a FIFO implementation the status of the RdFifoEmpty flag indicates if data is ready for reading, see also Read Buffer Status Register. You can use the RdFifoTide flag to indicate that a burst transfer of reads can occur, by setting the tide level to the number of words before the FIFO is empty. These two signals are defined events on the event bus. You can use them to enable the XVC to read the FIFO contents, either as a single read or reads from multiple FIFO registers. The XVC can directly read the contents of the registers, or RAMs, and then set the RdFifoRdPtr flag to the RdFifoWrPtr value, effectively setting the FIFO to empty, or increment the RdFifoRdPtr flag the number of reads performed.

In a DPRAM implementation then it is the responsibility of the XVC to ensure that the new data written is not going to overwrite the reading location. Because the XVC can access the memory in zero time this is not an issue. The RdFifoTide flag event is monitored by the XVC to determine when it can read data from the DPRAM. You can use the block size to generate an event when the block is full, and ready for reading. The RdBufControl register bits RdBlockSize sets the size of the block in words to generate the RdFifoTide event when that size is crossed, this size is a power of 2, and can be up to 64K Words.

Write buffer, from XVC to PI

In a FIFO implementation the status of the WrFifoFull flag indicates if space is available for writing, see also Write Buffer Status Register. You can use the WrFifoTide flag to indicate that a burst transfer write can occur, by setting tide level to the number of words before the FIFO is full. These two signals are defined events on the event bus and can be used to enable the XVC to write to the FIFO, either as a single write or writes to multiple FIFO registers. The XVC can directly write the contents of the registers, or RAMs it then sets the WrFifoWrPtr flag to the WrFifoRdPtr flag value, effectively setting the FIFO to full, or increments the WrFifoWrPtr flag by the number of writes performed.

In a DPRAM implementation then it is the responsibility of the XVC to ensure that the new data written is not going to overwrite the reading location. Because the XVC can access the memory in zero time this is not a problem. The WrFifoTide flag event is monitored by the XVC to determine when it can write data to the DPRAM. You can use the block size to generate an event when the block is empty and ready for writing. The WrBufControl Register bits WrBlockSize sets the size of the block in words to generate the WrFifoTide event when that size is crossed. This size is a power of 2 and can be up to 64k Words.

Copyright © 2005 ARM Limited. All rights reserved.ARM DDI 0364A
Non-Confidential