2.2.5. Register level interface

Figure 2.6 shows APB timing. The register level interface occupies 4K bits of address space per PTB. This bus uses the same timing as the APB, see the AMBA 2.0 specification, and can interface directly to the APB. Access to the registers is by 32 bit word transfers only, all other accesses are not permitted. A single 32 bit wide write bus and a 32 bit wide read bus are implemented. The required register is selected by the address input, 10 bits wide PADDR[12:2]. Figure 2.6 shows the basic timing for the APB 2.0 bus, see the AMBA 2.0 Specification section APB for more details of this timing.

Figure 2.6. APB 2.0 timing

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