3.3.27. Peripheral Identification Registers

The Peripheral Identification Registers are eight, 8-bit read-only registers. They span two address locations:

Each of these blocks of registers 0-3 and 4-7 can conceptually be treated as one 32-bit read-only register. The PeriphID0-3 Registers provide the peripheral options listed in Table 3-28.

Table 3.28. Peripheral Identification Register options, PeriphID0-3

BitsDescription
Configuration 1[31:24] The configuration option of the peripheral.
Revision number[23:20] The revision number of the peripheral. The revision number starts from 0.
Designer[19:12] The designer identification. ARM Limited is 0x41 (ASCII A).
Part number[11:0] The peripheral, using the three digit product code.

Note

When you design a systems memory map then you must remember that the register has a 4KB-memory footprint. All memory accesses to the Peripheral Identification Registers must be 32-bit, using the LDR and STR instructions.

Figure 3.11 shows the bit assignments for the IECPeriphID0-3 Registers.

Figure 3.11. Peripheral Identification Register bit assignments, PeriphID0-3

The PeriphID4-7 Registers provide the peripheral options listed in Table 3.29.

Table 3.29. Peripheral Identification Register options, PeriphID4-7

Bits Description
Configuration 5[31:24]Reserved, read undefined.
Configuration 4[23:16]Reserved, read undefined.
Configuration 3[15:8]Reserved, read undefined.
Configuration 2[7:0]Reserved, read undefined.

Figure 3.12 shows the bit assignments for the IECPeriphID4-7 Registers.

Figure 3.12. Peripheral Identification Register bit assignments, IECPeriphID4-7

The eight, 8-bit peripheral identification registers are described in the following subsections:

Peripheral Identification Register 0

The PeriphID0 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.30 lists the register bit assignments.

Table 3.30. IECPeriphID0 Register bit assignments

Bits Name Description
[31:8]-Reserved, read undefined.
[7:0 ]Partnumber 0See note.

Note

The Partnumber0 value is equal to the same value contained within the peripheral ID registers of the peripheral which the PTB accompanies. A unique part number is assigned for PTBs that are not designed to accompany a specific peripheral, for example, a system-level clock controller.

Peripheral Identification Register 1

The PeriphID1 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.31 lists the register bit assignments.

Table 3.31. PeriphID1 Register bit assignments

Bits Name Description
[31:8]-Reserved, read undefined.
[7:4 ]Designer0 These bits read back as 0x1.
[3:0 ]Partnumber1 See note.

Note

The Partnumber1 value is equal to the same value contained within the peripheral ID registers of the peripheral which the PTB accompanies. A unique part number is assigned for PTBs that are not designed to accompany a specific peripheral, for example, a system-level clock controller.

Peripheral Identification Register 2

The PeriphID2 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.32 lists the register bit assignments.

Table 3.32. PeripID2 Register bit assignments

Bits Name Description
[31:8]-Reserved, read undefined.
[7:4 ]Revision See note.
[3:0] Designer1 These bits read back as 0x4.

Note

The Revision value is equal to the same value contained within the peripheral ID registers of the peripheral which the PTB accompanies. The Revision is equal to 0x00 for PTBs that are not designed to accompany a specific peripheral, for example, a system-level clock controller.

Peripheral Identification Register 3

The PeriphID3 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.33 lists the register bit assignments.

Table 3.33. PeriphID3 Register bit assignments

Bits Name Description
[31:8]-Reserved, read undefined.
[7:0] Configuration 1These bits contain the revision number of the PTB.

Peripheral Identification Register 4

The PeriphID4 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.34 lists the register bit assignments.

Table 3.34. PeriphID4 Register bit assignments

BitNameDescription
[31:8]-Reserved, read undefined.
[7:0]Configuration 2These bits are all reserved.

Peripheral Identification Register 5

The PeriphID5 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.35 lists the register bit assignments

Table 3.35. PeriphID5 Register bit assignments

Bits Name Description
[31:8]-Reserved, read undefined.
[7:0 ]Configuration 3These bits are all reserved.

Peripheral Identification Register 6

The PeriphID6 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.36 lists the register bit assignments

Table 3.36. PeriphID6 Register bit assignments

Bits Name Description
[31:8]-Reserved, read undefined.
[7:0 ]Configuration 4These bits are all reserved.

Peripheral Identification Register 7

The PeriphID7 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.37 lists the register bit assignments

Table 3.37. PeriphID7 Register bit assignments

Bits Name Description
[31:8]-Reserved, read undefined.
[7:0 ]Configuration 5These bits are all reserved.
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