3.2. Summary of registers

All register addresses in the PTB are fixed relative to the base address. Table 3.1 lists the registers in base offset order:

Table 3.1. Summary of Peripheral Test Block registers

NameBase offsetTypeReset valueDescription
EventMaskedStatus0x000RO0x00000000See Event Masked Status Register
EventMask0x004R/W0x00000000See Event Mask Register
EventRawStatus0x008RO0x00000000See Raw Event Status Register
EventClear0x00CR/W0x00000000See Event Clear Register
DmaclntrControl0x010R/W0x00000000See Direct Memory Access Controller Register
Xfer0x014R/W0x00000000See Xfer Register
ctr100x100R/W0x00000000See Control0 Register
ctrl10x104R/W0x00000000See Control1 Register
Sts00x200RO0x00000000See Status0 Register
Sts10x204RO0x00000000See Status1 Register
RdBufStatus0x300RO0x00000000See Read Buffer Status Register
RdBufControl0x304R/W0x00000000See Read Buffer Control Register
RdBufPTIStAddr0x308R/W0x00000000See Read Buffer PTI Start Address Register
RdBufPIStAddr0x30CR/W0x00000000See Read Buffer PI Start Address Register
RdBufPTIAddr0x310RO0x00000000See Read Buffer PTI Present Address Register
RdBufPIAddr0x314RO0x00000000See Read Buffer PI Start Address Register
WrBufStatus0x400RO0x00000000See Write Buffer Status Register
WrBufControl0x404R/W0x00000000See Write Buffer Control Register
WrBufPTIStAddr0x408R/W0x00000000See Write Buffer PTI Start Address Register
WrBufPIStAddr0x40CR/W0x00000000See Write Buffer PI Start Address Register
WrBufPTIAddr0x410RO0x00000000See Write Buffer PTI Present Address Register
WrBufPIAddr0x414RO0x00000000See Write Buffer PI Start Address Register
RdBufData00x500RO0x00000000See Read Buffer Data0 Register
RdBufData10x504RO0x00000000See Read Buffer Data1 Register
WrBufData00x600WO0x00000000See Write Buffer Data0 Register
WrBufData10x604WO0x00000000See Write Buffer Data1 Register
PeriphID40xFD0RO0x00000000See Peripheral Identification Register 4
PeriphID50xFD4RO0x00000000See Peripheral Identification Register 5
PeriphID60xFD8RO0x00000000See Peripheral Identification Register 6
PeriphID70xFDCRO0x00000080See Peripheral Identification Register 7
PeriphID00xFE0RO0x00000000See Peripheral Identification Register 0
PeriphID10xFE4RO0x00000010See Peripheral Identification Register 1
PeriphID20xFE8RO0x00000004See Peripheral Identification Register 3
PeriphID30xFECRO0x00000000See Peripheral Identification Register 3
CompID00xFF0RO0x0000000DSee Component Identification Register 0
CompID10xFF4RO0x000000F0See Component Identification Register 1
CompID20xFF8RO0x00000005See Peripheral Identification Register 2
CompID30xFFCRO0x000000B1See Component Identification Register 3


If required, the address space from 0x0000 1000 to 0xFFFF is available for the mapping of a Dual Ported RAM (DPRAM). This can be accessed by using the single or incrementing mode.

Copyright © 2005 ARM Limited. All rights reserved.ARM DDI 0364A