The base address of the PTB is not fixed, and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.

Reserved or unused address locations must not be accessed because this can result in unpredictable behavior of the device.

Reserved or unused bits of registers must be written as zero, and ignored on read unless otherwise stated in the relevant text.

All register bits are reset to a logic 0 by a system or power-on reset unless otherwise stated in the relevant text.

All registers support read and write accesses unless otherwise stated in the relevant text. A write updates the contents of a register and a read returns the contents of the register.