Peripheral Test Block Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on the product
Feedback on this manual
1. Introduction
1.1. PrimeCell types
1.2. PTB overview
1.3. Validation environments
1.3.1. Directed, integration and system environments
1.3.2. XVC environment
1.3.3. Platform
2. Functional Overview
2.1. Functional description
2.2. Functional operation
2.2.1. PTB internal structure
2.2.2. Transferring data between clock domains
2.2.3. XVC data transfer
2.2.4. Peripheral test wrapper
2.2.5. Register level interface
2.2.6. Peripheral test interface bus
2.2.7. FIFO options for usage models
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Summary of registers
3.3. Register descriptions
3.3.1. Event Masked Status Register
3.3.2. Event Mask Register
3.3.3. Raw Event Status Register
3.3.4. Event Clear Register
3.3.5. Direct Memory Access Controller Register
3.3.6. Xfer Register
3.3.7. Control0 Register
3.3.8. Control1 Register
3.3.9. Status0 Register
3.3.10. Status1 Register
3.3.11. Read Buffer Status Register
3.3.12. Read Buffer Control Register
3.3.13. Read Buffer PTI Start Address Register
3.3.14. Read Buffer PI Start Address Register
3.3.15. Read Buffer PTI Present Address Register
3.3.16. Read Buffer PI Start Address Register
3.3.17. Write Buffer Status Register
3.3.18. Write Buffer Control Register
3.3.19. Write Buffer PTI Start Address Register
3.3.20. Write Buffer PI Start Address Register
3.3.21. Write Buffer PTI Present Address Register
3.3.22. Write Buffer PI Start Address Register
3.3.23. Read Buffer Data0 Register
3.3.24. Read Buffer Data1 Register
3.3.25. Write Buffer Data0 Register
3.3.26. Write Buffer Data1 Register
3.3.27. Peripheral Identification Registers
3.3.28. Component Identification Registers
Glossary

List of Tables

2.1. PTIB address map
3.1. Summary of Peripheral Test Block registers
3.2. EventMaskedStatus Register bit assignments
3.3. EventMask Register bit assignments
3.4. EventRawStatus Register bit assignments
3.5. EventClear Register bit assignments
3.6. DmaclntrControl Register bit assignments
3.7. Xfer Register bit assignments
3.8. Ctrl0 Register bit assignments
3.9. Ctrl1 Register bit assignments
3.10. Sts0 Register bit assignments
3.11. Sts1 Register bit assignments
3.12. RdBufStatus Register bit assignments
3.13. RdBufControl Register bit assignments
3.14. RdBufPTIStAddr Register bit assignments
3.15. RdBufPIStAddr Register bit assignments
3.16. RdBufPTIAddr Register bit assignments
3.17. RdBufPIAddr Register bit assignments
3.18. WrBufStatus Register bit assignments
3.19. WrBufControl Register bit assignments
3.20. WrBufPTIStAddr Register bit assignments
3.21. WrBufPIStAddr Register bit assignments
3.22. WrBufPTIAddr Register bit assignments
3.23. WrBufPIAddr Register bit assignments
3.24. RdBufData0 Register bit assignments
3.25. RdBufData1 Register bit assignments
3.26. WrBufData0 Register bit assignments
3.27. WrBufData1 Register bit assignments
3.28. Peripheral Identification Register options, PeriphID0-3
3.29. Peripheral Identification Register options, PeriphID4-7
3.30. IECPeriphID0 Register bit assignments
3.31. PeriphID1 Register bit assignments
3.32. PeripID2 Register bit assignments
3.33. PeriphID3 Register bit assignments
3.34. PeriphID4 Register bit assignments
3.35. PeriphID5 Register bit assignments
3.36. PeriphID6 Register bit assignments
3.37. PeriphID7 Register bit assignments
3.38. Component Identification Register options, PeriphID0-3
3.39. CompID0 Register bit assignments
3.40. CompID1 Register bit assignments
3.41. PeripID2 Register bit assignments
3.42. PeriphID3 Register bit assignments

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A01 February 2005First release
Copyright © 2005 ARM Limited. All rights reserved.ARM DDI 0364A
Non-Confidential