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Home > I/O Signal Timings > ETMR4 I/O timing parameters |
Signals are classified according to the percentage of the clock period taken up by internal logic.
For inputs this is the delay between the input port and the first register.
For outputs this is the delay between the last register and the output port.
The timing classifications used are based on these delays:
The delay is less than 20% of the period.
The delay is between 20% and 80% of the period.
The delay is greater than 80% of the period.
Table B.1 describes the ETMR4 signal timing parameters.
Table B.1. ETMR4 signal timing parameters
Signal name | Timing classification | Input/Output |
---|---|---|
AFREADY | Middle | Output |
AFVALID | Middle | Input |
ASICCTL[7:0] | Middle | Output |
ATBYTES[1:0] | Middle | Output |
ATCLK | - | Input |
ATCLKEN | Middle | Input |
ATDATA[31:0] | Middle | Output |
ATID[6:0] | Middle | Output |
ATREADY | Middle | Input |
ATVALID | Middle | Output |
CLK | - | Input |
CORESELECT[2:0] | Middle | Output |
DBGACK | Middle | Input |
DBGEN | Middle | Input |
ETMCID[31:0] | Middle | Input |
ETMDA[31:0] | Middle | Input |
ETMDBGRQ | Middle | Output |
ETMDD[63:0] | Middle | Input |
ETMDCTL[11:0] | Middle | Input |
ETMEN | Middle | Output |
ETMIA[31:1] | Middle | Input |
ETMICTL[13:0] | Middle | Input |
ETMPWRUP | Middle | Output |
ETMWFIPENDING | Middle | Input |
EVNTBUS[46:0] | Middle | Input |
EXTIN[3:0] | Middle | Input |
EXTOUT[1:0] | Middle | Output |
FIFOPEEK[6:0] | Middle | Output |
MAXCORES[2:0] | Middle | Input |
MAXEXTIN[2:0] | Middle | Input |
MAXEXTOUT[1:0] | Middle | Input |
nETMWFIREADY | Middle | Output |
NIDEN | Middle | Input |
PADDRDBG[11:2] | Middle | Input |
PADDRDBG31 | Middle | Input |
PCLKDBG | Middle | Input |
PCLKENDBG | Middle | Input |
PENABLEDBG | Middle | Input |
PRDATADBG[31:0] | Middle | Output |
PREADYDBG | Late | Output |
PRESETDBGn | Late | Input |
PSELDBG | Middle | Input |
PWDATADBG[31:0] | Middle | Input |
PWRITEDBG | Middle | Input |
RSTBYPASS | Middle | Input |
SE | Middle | Input |
nSYSPORESET | Middle | Input |
TRIGGER | Middle | Output |
TRIGGERACK | Middle | Input |
TRIGSBYPASS | Middle | Input |
Actual clock frequencies and input and output timing constraints vary according to application requirements and the silicon process technologies used. The maximum operating clock frequencies change according to the constraints and the process technology you use.