A.1. ETMR4 Signals

Table A.1 shows the ETMR4 signals in alphabetical order. Clock domains, where specified, give the clock on which input signals must be generated and output signals sampled. See the CoreSight ETM‑R4 Integration Manual for information about signals and connectivity.

Table A.1. ETMR4 signals

SignalInput/outputDescriptionClock domain
AFREADYOutputATB interface FIFO flush finished.ATCLK
AFVALIDInputATB interface FIFO flush request.ATCLK
ASICCTL[7:0]OutputContents of the ASIC control register, ASICCTL.CLK
ATBYTES[1:0]OutputSize of ATDATA.ATCLK
ATCLKInputATB interface clock.-
ATCLKENInputEnable signal for ATCLK. ATCLK
ATDATA[31:0]OutputATB interface data.ATCLK
ATID[6:0]OutputATB interface trace source ID.ATCLK
ATREADYInputATDATA can be accepted.ATCLK
ATVALIDOutput ATB interface data valid.ATCLK
CLKInputThis is the main clock for the ETMR4.-
CORESELECT[2:0]Output

Where an ETM is shared between multiple cores, this signal specifies which core to trace.

The value appears as bits [14:12] of the System Configuration Register.

CLK
DBGACKInput

Indicates that the core is in debug state.

This signal is connected to the core general purpose DBGACK output, so that it can be used to determine when ETMDBGRQ can be deasserted. It is also used for other purposes in the ETM, and care must be taken to ensure the timing of this signal is appropriate because it does not come through the main interface between the core and the ETM.

CLK
DBGENInput

Invasive debug enable.

When HIGH (1), indicates that invasive debug is enabled.

If this signal and NIDEN are both LOW, CLK and ATCLK are both stopped and no trace is generated.

-
ETMCID[31:0]Input

Current value of the processor Context ID Register.

CLK
ETMDA[31:0]InputAddress for data transfer.CLK
ETMDBGRQOutputRequest from the macrocell for the core to enter debug state. This must be ORed with any ASIC-level DBGRQ signals before being connected to the core EDBGRQ input.CLK
ETMDD[63:0]InputContains the data value for a Load, Store, MRC, or MCR instruction.CLK
ETMDCTL[11:0]InputData control signals.CLK
ETMENOutputEnable signal for trace output from the ETM, driven by bit [11] of the ETM Control Register.CLK
ETMIA[31:1]InputAddress for executed instruction.CLK
ETMICTL[13:0]InputInstruction control signals.CLK
ETMPWRUPOutput

When HIGH, indicates that the macrocell is in use.

When LOW:

  • external logic supporting the macrocell can be clock-gated to conserve power

  • the Cortex‑R4 processor disables the interface

  • logic within the macrocell is clock-gated to conserve power.

CLK
ETMWFIPENDINGInputIndicates that the Cortex‑R4 processor is about to go into Standby mode, and that the ETM must drain its FIFO.CLK
EVNTBUS[46:0]InputGives the status of the performance monitoring events. Used as extended external inputs.CLK
EXTIN[3:0]InputExternal input resources.CLK
EXTOUT[1:0]OutputExternal outputs.CLK
FIFOPEEK[6:0]Output

For validation purposes only.

Indicates when various events occur before being written to the FIFO.

CLK
MAXCORES[2:0]Input

Where an ETM is shared between multiple cores, this signal specifies the number of cores the ETM can trace. It must be tied to the number of cores sharing the ETM minus 1.

These signals determine the value of bits [14:12] of the System Configuration register, see the footnote to Table 3.1.

CLK
MAXEXTIN[2:0]Input

Number of external inputs supported by the ASIC (maximum 4).

These signals determine the value bits [19:17] in the Configuration Code Register, see Configuration Code Register.

CLK
MAXEXTOUT[1:0]Input

Number of external outputs supported by the ASIC (maximum 2).

These signals determine the value bits [22:20] in the Configuration Code Register, see Configuration Code Register.

CLK
nETMWFIREADYOutputIndicates that the macrocell FIFO is empty and that the Cortex‑R4 processor can be put into Standby mode.CLK
NIDENInput

Non-invasive debug enable.

When HIGH (1), indicates that non-invasive debug is enabled.

If this signal and DBGEN are both LOW, CLK and ATCLK are both stopped and no trace is generated.

-
PADDRDBG[11:2]InputDebug APB Address Bus.PCLKDBG
PADDRDBG31Input

Originates as an output signal from the Debug Access Port (DAP):

  • PADDRDBG31 at logic 1 indicates an access from hardware (JTAG)

  • PADDRDBG31 at logic 0 indicates an access from software.

PCLKDBG
PCLKDBGInputDebug APB clock.-
PCLKENDBGInputDebug APB clock enable.PCLKDBG
PENABLEDBGInputThe Debug APB interface is enabled for a transfer.PCLKDBG
PRDATADBG[31:0]OutputDebug APB read data.PCLKDBG
PREADYDBGOutputUsed to extend Debug APB transfers.PCLKDBG
PRESETDBGnInput

Debug APB interface reset.

Resets all registers.

Internally synchronized
PSELDBGInputDebug APB slave select signal.PCLKDBG
PWDATADBG[31:0]InputDebug APB write data.PCLKDBG
PWRITEDBGInputDebug APB transfer direction, !Read/Write.PCLKDBG
RSTBYPASSInputReset synchronization bypass DFT signal.-
SEInputScan enable DFT signal-
nSYSPORESETInput

Power-on (main) reset.

Resets all registers.

Internally synchronized
TRIGGEROutputTrigger request status signal.ATCLK
TRIGGERACKInputATB trigger acknowledge.Internally synchronized
TRIGSBYPASSInputTrigger synchronization bypass.ATCLK
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