C.1.2. APB write transfer with wait states

Figure C.2 shows how the PREADY signal from the slave can extend the transfer. During an access cycle, when PENABLE is HIGH, the transfer can be extended by driving PREADY LOW. The following signals remain unchanged for the additional cycles:

Figure C.2. APB write transfer with wait states

PREADY can take any value when PENABLE is LOW. This ensures that peripherals that have a fixed two cycle access can tie PREADY HIGH.


It is recommended that the address and write signals are not changed immediately after a transfer but remain stable until another access occurs. This reduces power consumption.

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