C.1.1. APB write transfer with no wait states

Figure C.1 shows a basic write transfer with no wait states. The transfer starts with the address, write data, write signal, and select signal changing after the rising edge of the clock at T1. This is called the set-up cycle.

Figure C.1. APB write transfer with no wait states

After the following clock edge at T2, the enable signal, PENABLE, is asserted. This indicates that the access cycle is taking place. The address, data, and control signals remain valid throughout the access cycle and the transfer completes at the end of this cycle.

The enable signal, PENABLE, is deasserted at the end of the transfer. The select signal, PSELx, also goes LOW unless the transfer is to be followed immediately by another transfer to the same peripheral.


PSELx indicates that the slave device is selected and that a data transfer is required.There is a PSELx signal for each slave.

Copyright © 2005, 2007 ARM Limited. All rights reserved.ARM DDI 0367B