3.5.4. ETM ID Register

The ETM ID Register has value 0x4104F231, and is read-only. Figure 3.5 shows the arrangement of bits in the register.

Figure 3.5. ETM ID Register bit assignments

Table 3.11 lists how the bit values correspond with the register functions in the macrocell. The ETM ID Register has the value 0x4104F23x, where x depends on the release version of the macrocell, see the Implementation revision field description in the table for more information.

Table 3.11. ETM ID Register bit assignments

Bit numbersValueFunction
[31:24]0x41Implementor = A (for ARM).
[23:20]b0000Reserved.
[19]0

Security Extensions support. This bit is set to 1 if the processor supports the ARMv7 architecture Security Extensions.

On the macrocell, this bit is not set (=0), meaning that the ETM behaves as if the processor is in Secure state at all times.

[18]1

Thumb-2 support. This bit is set to 1 if the processor supports the Thumb-2 architectural extensions.

On the macrocell, this bit is set to 1, meaning that all 32-bit Thumb instructions are traced as a single instruction, including BL and BLX immediate.

[17]0Reserved.
[16]0

If set to 1, load PC first.

On the macrocell, this bit is not set (=0), meaning that on an LSM[1] load operation with the PC included in the load list, the PC is not loaded first.

[15:12]b1111

ARM processor family.

The value of b1111 means that the processor family is defined elsewhere.

[11:8]b0010

Major ETM architecture version number. A value of 0 in this field indicates ETMv1.

For ETM v3.x, this field = 2.

[7:4]b0011

Minor ETM architecture version number.

For ETM v x.3, this field = 3.

[3:0]b0001Implementation revision. Value given is for the r1p0 release of the macrocell. For release r0p0 the value is b0000.

[1] See the ETM Architecture Specification for a definition and list of LSM operations.

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