3.5.2. Configuration Code Register

The Configuration Code Register, 0x001 at offset 0x004, is read-only. Figure 3.3 shows the arrangement of bits in the register.

Figure 3.3. Configuration Code Register bit assignments

Table 3.9 lists how the bit values correspond with the register functions. If the MAXEXTOUT[1:0] and MAXEXTIN[2:0] signals are all tied LOW (0) the Configuration Code Register has the value 0x8D014024.

Table 3.9. Configuration Code Register bit assignments

BitsValueFunction
[31]1ETM ID Register present.
[30:28]b000Reserved. Read-As-Zero (RAZ).
[27]1Software access is supported.
[26]1Trace start/stop block is present.
[25:24]1Number of Context ID comparators.
[23]0FIFOFULL logic absent.
[22]0

Reserved, Read-As-Zero.

The ETM Architecture Specification defines this as the most significant bit of the Number of external outputs field, see the description of bits [21:20].

[21:20]-

Number of external outputs. Determined by the MAXEXTOUT[1:0] inputs.

The value of these bits is the minimum of MAXEXTOUT[1:0] and 2, because CoreSight ETM‑R4 supports a maximum of 2 external outputs.

[19:17]-

Number of external inputs. Determined by the MAXEXTIN[2:0] inputs.

The value of these bits is the minimum of MAXEXTIN[2:0] and 4, because CoreSight ETM‑R4 supports a maximum of 4 external inputs.

[16]1The sequencer is present.
[15:13]2Number of counters.
[12:8]0Number of memory map decoders.
[7:4]2Number of data comparators.
[3:0]4Number of pairs of address comparators.
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