3.4.1. List of registers in numerical order

Table 3.1 shows all of the registers, and tells you where each register is described in detail. The registers are listed in register number order.

The macrocell registers are listed by functional group in the section Functional grouping of registers. The functional group register tables include additional information about each register:


  • Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.

  • In Table 3.1:

    • the Default value column shows the value of the register immediately after an ETM reset. For read-only registers, every read of the register returns this value.

    • the listed Functional group table gives more information about the register, including whether it is read-only, read/write, or write-only,

Table 3.1. ETM registers summary

NameRegister numberAccessDefault valueGroup [1]Description, see
ETM Control0x000R/W0x000004411ETM Control Register
Configuration Code0x001RO0x8D014024 [2]1Configuration Code Register
Trigger Event0x002R/W- [3]4ETM Architecture Specification
ASIC Control0x003R/W- [3]1ASIC Control Register
ETM Status0x004R/W- [3]1ETM Architecture Specification
System Configuration0x005RO0x00020C0C [4]1ETM Architecture Specification
TraceEnable Start/Stop Resource control0x006R/W- [3]2ETM Architecture Specification
TraceEnable Control 20x007R/W- [3]2ETM Architecture Specification
TraceEnable Event0x008R/W- [3]2ETM Architecture Specification
TraceEnable Control 10x009R/W- [3]2ETM Architecture Specification
FIFOFULL Level[5]0x00BR/W- [3]1ETM Architecture Specification
ViewData Event0x00CR/W- [3]2ETM Architecture Specification
ViewData Control 10x00DR/W- [3]2ETM Architecture Specification
ViewData Control 30x00FR/W- [3]2ETM Architecture Specification
Address Comparator Value 1 - 80x010 to 0x017R/W- [3]3ETM Architecture Specification
Address Comparator Access Type 1 - 80x020 to 0x027R/W- [3]3ETM Architecture Specification
Data Comparator Value 1[6]0x030[6]R/W- [3]3ETM Architecture Specification
Data Comparator Value 3[6]0x032[6]R/W- [3]3ETM Architecture Specification
Data Comparator Mask 1[6]0x040[6]R/W- [3]3ETM Architecture Specification
Data Comparator Mask 3[6]0x042[6]R/W- [3]3ETM Architecture Specification
Counter Reload Value 1 - 20x050, 0x051R/W- [3]4ETM Architecture Specification
Counter Enable Event 1 - 20x054, 0x055R/W- [3]4ETM Architecture Specification
Counter Reload Event 1 - 20x058, 0x059R/W- [3]4ETM Architecture Specification
Counter Value 1 - 20x05C, 0x05DR/W- [3]4ETM Architecture Specification
Sequencer State Transition Events0x060 to 0x065R/W- [3]4ETM Architecture Specification
Current Sequencer State0x067R/W- [3]4ETM Architecture Specification
External Output Event 1 - 20x068, 0x069R/W- [3]4ETM Architecture Specification
Context ID Comparator Value0x06CR/W- [3]3ETM Architecture Specification
Context ID Comparator Mask0x06FR/W- [3]3ETM Architecture Specification
Synchronization Frequency0x078R/W0x000004001ETM Architecture Specification
ETM ID0x079RO0x4104F23x [7]1ETM ID Register
Configuration Code Extension0x07ARO0x0000097A1Configuration Code Extension Register
Extended External Input Selector0x07BR/W- [3]4Extended External Input Selection Register
CoreSight Trace ID0x080R/W0x000000001See ETM Architecture Specification
Power-Down Status register0x0C5RO- [3]1Power-Down Status register
ITETMIF0x3B6RO [8]-[9]6ITETMIF Register, ETM interface
ITMISCOUT0x3B7WOn/a [10]6ITMISCOUT Register, miscellaneous outputs
ITMISCIN0x3B8RO [8]- [9]6ITMISCIN Register, miscellaneous inputs
ITTRIGGERACK0x3B9RO [8]- [9]6ITTRIGGERACK Register, trigger acknowledge
ITTRIGGERREQ0x3BAWOn/a [10]6ITTRIGGERREQ Register, trigger request
ITATBDATA00x3BBWOn/a [10]6ITATBDATA0 Register, ATB data 0
ITATBCTR20x3BCRO [8]- [9]6ITATBCTR2 Register, ATB control 2
ITATBCTR10x3BDWOn/a [10]6ITATBCTR1 Register, ATB control 1
ITATBCTR00x3BEWOn/a [10]6ITATBCTR0 Register, ATB control 0
Integration Mode Control0x3C0R/W0x000000005ETM Architecture Specification
Claim Tag Set0x3E8R/W0x000000FF5ETM Architecture Specification
Claim Tag Clear0x3E9R/W0x000000005ETM Architecture Specification
Lock Access0x3ECWOn/a [10]5ETM Architecture Specification
Lock Status0x3EDRO- [9]5ETM Architecture Specification
Authentication Status0x3EERO- [9]5ETM Architecture Specification
Device Configuration0x3F2RO0x000000005ETM Architecture Specification
Device Type0x3F3RO0x000000135ETM Architecture Specification
Peripheral ID4 to 70x3F4 to 0x3F7RO- [9]5Peripheral Identification Registers
Peripheral ID0 to 30x3F8 to 0x3FBRO- [9]
Component ID0 to 30x3FC to 0x3FFRO- [9]5Component Identification Registers

[1] Functional group. For more information, see:

        for Group 1, Table 3.2, Table 3.2

        for Group 2, Table 3.3, Table 3.3

        for Group 3, Table 3.4, Table 3.4

        for Group 4, Table 3.5, Table 3.5

        for Group 5, Table 3.6, Table 3.6

        for Group 5, Table 3.7, Table 3.7.

[2] Default value when MAXEXTOUT[1:0] and MAXEXTIN[2:0] are all tied LOW (0), see the register description for more information.

[3] These registers are not reset by a reset of the macrocell. Therefore, they do not have specific default values.

[4] Bits [14:12] of the System Configuration Register are tied to the MAXCORES[2:0] signals. If a MAXCORES bit is High then the corresponding bit in the System Configuration Register is set to 1, for example if MAXCORES[0] is tied HIGH then bit [12] is set to 1. The default value given is for all MAXCORES signals tied LOW, bits [14:12] = b000.

For more information about the MAXCORES[2:0] signals, see ETMR4 Signals

[5] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the ETM Architecture Specification.

[6] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM‑R4, reserved areas are:

   Register 0x031, Data Comparator Value 1, at offset 0x0C4     Register 0x033, Data Comparator Value 3, at offset 0x0CC

   Register 0x041, Data Comparator Mask 1, at offset 0x104     Register 0x043, Data Comparator Mask 3, at offset 0x10C.

You must not write to these reserved register addresses. Reads from these addresses are Unpredictable.

[7] The value of bits [3:0] of the ETM ID Register depend on the macrocell revision, see the register description for more information.

[8] The values of the read-only Integration Test registers are valid only when the macrocell is in Integration Test mode. If you read one of these registers when the macrocell is in normal operating mode the result returned is Unknown.

[9] See the register description for details.

[10] Not applicable. These are write-only registers.

Copyright © 2005, 2007 ARM Limited. All rights reserved.ARM DDI 0367B