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Home > Programmer’s Model > Summary of ETM registers > List of registers in numerical order |
Table 3.1 shows all of the registers, and tells you where each register is described in detail. The registers are listed in register number order.
The macrocell registers are listed by functional group in the section Functional grouping of registers. The functional group register tables include additional information about each register:
The register access type. This is read-only, write-only or read/write.
The clock domain of the register.
The base offset address of the register. The base address of a register is always four times its register number.
Additional information about the implementation of the register, where appropriate.
Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.
In Table 3.1:
the Default value column shows the value of the register immediately after an ETM reset. For read-only registers, every read of the register returns this value.
the listed Functional group table gives more information about the register, including whether it is read-only, read/write, or write-only,
Table 3.1. ETM registers summary
Name | Register number | Access | Default value | Group [1] | Description, see |
---|---|---|---|---|---|
ETM Control | 0x000 | R/W | 0x00000441 | 1 | ETM Control Register |
Configuration Code | 0x001 | RO | 0x8D014024 [2] | 1 | Configuration Code Register |
Trigger Event | 0x002 | R/W | - [3] | 4 | ETM Architecture Specification |
ASIC Control | 0x003 | R/W | - [3] | 1 | ASIC Control Register |
ETM Status | 0x004 | R/W | - [3] | 1 | ETM Architecture Specification |
System Configuration | 0x005 | RO | 0x00020C0C [4] | 1 | ETM Architecture Specification |
TraceEnable Start/Stop Resource control | 0x006 | R/W | - [3] | 2 | ETM Architecture Specification |
TraceEnable Control 2 | 0x007 | R/W | - [3] | 2 | ETM Architecture Specification |
TraceEnable Event | 0x008 | R/W | - [3] | 2 | ETM Architecture Specification |
TraceEnable Control 1 | 0x009 | R/W | - [3] | 2 | ETM Architecture Specification |
FIFOFULL Level[5] | 0x00B | R/W | - [3] | 1 | ETM Architecture Specification |
ViewData Event | 0x00C | R/W | - [3] | 2 | ETM Architecture Specification |
ViewData Control 1 | 0x00D | R/W | - [3] | 2 | ETM Architecture Specification |
ViewData Control 3 | 0x00F | R/W | - [3] | 2 | ETM Architecture Specification |
Address Comparator Value 1 - 8 | 0x010 to 0x017 | R/W | - [3] | 3 | ETM Architecture Specification |
Address Comparator Access Type 1 - 8 | 0x020 to 0x027 | R/W | - [3] | 3 | ETM Architecture Specification |
Data Comparator Value 1[6] | 0x030 [6] | R/W | - [3] | 3 | ETM Architecture Specification |
Data Comparator Value 3[6] | 0x032 [6] | R/W | - [3] | 3 | ETM Architecture Specification |
Data Comparator Mask 1[6] | 0x040 [6] | R/W | - [3] | 3 | ETM Architecture Specification |
Data Comparator Mask 3[6] | 0x042 [6] | R/W | - [3] | 3 | ETM Architecture Specification |
Counter Reload Value 1 - 2 | 0x050 , 0x051 | R/W | - [3] | 4 | ETM Architecture Specification |
Counter Enable Event 1 - 2 | 0x054 , 0x055 | R/W | - [3] | 4 | ETM Architecture Specification |
Counter Reload Event 1 - 2 | 0x058 , 0x059 | R/W | - [3] | 4 | ETM Architecture Specification |
Counter Value 1 - 2 | 0x05C , 0x05D | R/W | - [3] | 4 | ETM Architecture Specification |
Sequencer State Transition Events | 0x060 to 0x065 | R/W | - [3] | 4 | ETM Architecture Specification |
Current Sequencer State | 0x067 | R/W | - [3] | 4 | ETM Architecture Specification |
External Output Event 1 - 2 | 0x068 , 0x069 | R/W | - [3] | 4 | ETM Architecture Specification |
Context ID Comparator Value | 0x06C | R/W | - [3] | 3 | ETM Architecture Specification |
Context ID Comparator Mask | 0x06F | R/W | - [3] | 3 | ETM Architecture Specification |
Synchronization Frequency | 0x078 | R/W | 0x00000400 | 1 | ETM Architecture Specification |
ETM ID | 0x079 | RO | 0x4104F23x [7] | 1 | ETM ID Register |
Configuration Code Extension | 0x07A | RO | 0x0000097A | 1 | Configuration Code Extension Register |
Extended External Input Selector | 0x07B | R/W | - [3] | 4 | Extended External Input Selection Register |
CoreSight Trace ID | 0x080 | R/W | 0x00000000 | 1 | See ETM Architecture Specification |
Power-Down Status register | 0x0C5 | RO | - [3] | 1 | Power-Down Status register |
ITETMIF | 0x3B6 | RO [8] | -[9] | 6 | ITETMIF Register, ETM interface |
ITMISCOUT | 0x3B7 | WO | n/a [10] | 6 | ITMISCOUT Register, miscellaneous outputs |
ITMISCIN | 0x3B8 | RO [8] | - [9] | 6 | ITMISCIN Register, miscellaneous inputs |
ITTRIGGERACK | 0x3B9 | RO [8] | - [9] | 6 | ITTRIGGERACK Register, trigger acknowledge |
ITTRIGGERREQ | 0x3BA | WO | n/a [10] | 6 | ITTRIGGERREQ Register, trigger request |
ITATBDATA0 | 0x3BB | WO | n/a [10] | 6 | ITATBDATA0 Register, ATB data 0 |
ITATBCTR2 | 0x3BC | RO [8] | - [9] | 6 | ITATBCTR2 Register, ATB control 2 |
ITATBCTR1 | 0x3BD | WO | n/a [10] | 6 | ITATBCTR1 Register, ATB control 1 |
ITATBCTR0 | 0x3BE | WO | n/a [10] | 6 | ITATBCTR0 Register, ATB control 0 |
Integration Mode Control | 0x3C0 | R/W | 0x00000000 | 5 | ETM Architecture Specification |
Claim Tag Set | 0x3E8 | R/W | 0x000000FF | 5 | ETM Architecture Specification |
Claim Tag Clear | 0x3E9 | R/W | 0x00000000 | 5 | ETM Architecture Specification |
Lock Access | 0x3EC | WO | n/a [10] | 5 | ETM Architecture Specification |
Lock Status | 0x3ED | RO | - [9] | 5 | ETM Architecture Specification |
Authentication Status | 0x3EE | RO | - [9] | 5 | ETM Architecture Specification |
Device Configuration | 0x3F2 | RO | 0x00000000 | 5 | ETM Architecture Specification |
Device Type | 0x3F3 | RO | 0x00000013 | 5 | ETM Architecture Specification |
Peripheral ID4 to 7 | 0x3F4 to 0x3F7 | RO | - [9] | 5 | Peripheral Identification Registers |
Peripheral ID0 to 3 | 0x3F8 to 0x3FB | RO | - [9] | ||
Component ID0 to 3 | 0x3FC to 0x3FF | RO | - [9] | 5 | Component Identification Registers |
[1] Functional group. For more information, see: for Group 1, Table 3.2, Table 3.2 for Group 2, Table 3.3, Table 3.3 for Group 3, Table 3.4, Table 3.4 for Group 4, Table 3.5, Table 3.5 [2] Default value when MAXEXTOUT[1:0] and MAXEXTIN[2:0] are all tied LOW (0), see the register description for more information. [3] These registers are not reset by a reset of the macrocell. Therefore, they do not have specific default values. [4] Bits [14:12] of the System Configuration Register are tied to the MAXCORES[2:0] signals. If a MAXCORES bit is High then the corresponding bit in the System Configuration Register is set to 1, for example if MAXCORES[0] is tied HIGH then bit [12] is set to 1. The default value given is for all MAXCORES signals tied LOW, bits [14:12] = b000. For more information about the MAXCORES[2:0] signals, see ETMR4 Signals [5] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the ETM Architecture Specification. [6] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM‑R4, reserved areas are: Register Register You must not write to these reserved register addresses. Reads from these addresses are Unpredictable. [7] The value of bits [3:0] of the ETM ID Register depend on the macrocell revision, see the register description for more information. [8] The values of the read-only Integration Test registers are valid only when the macrocell is in Integration Test mode. If you read one of these registers when the macrocell is in normal operating mode the result returned is Unknown. [9] See the register description for details. [10] Not applicable. These are write-only registers. |