3.4.2. Functional grouping of registers

This section lists the macrocell registers by functional group, as follows:

These functional groups include all of the registers.

General control and ID registers

Table 3.2 shows the General Control and ID registers.

Table 3.2. General Control and ID registers

NameRegister numberBase offsetClock domainDescription, see
ETM Control0x0000x000CLKETM Control Register
Configuration Code0x0010x004CLKConfiguration Code Register
ASIC Control0x0030x00CCLKASIC Control Register
ETM Status0x0040x010CLKETM Architecture Specification.
System Configuration0x0050x014CLKETM Architecture Specification.
FIFOFULL Level[1]0x00B0x02CCLKETM Architecture Specification.
Synchronization Frequency0x0780x1E0CLKETM Architecture Specification.[2]
ETM ID0x0790x1E4CLKETM ID Register
Configuration Code Extension0x07A0x1E8CLKConfiguration Code Extension Register
CoreSight Trace ID0x0800x200CLKETM Architecture Specification.
Power-Down Status register0x0C50x314CLKPower-Down Status register

[1] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the ETM Architecture Specification.

[2] Only bits [11:2] of the Synchronization Frequency Register are implemented. Bits [1:0] Read-As-Zero.

TraceEnable and ViewData registers

Table 3.3 shows the TraceEnable and ViewData registers.

Table 3.3. TraceEnable and ViewData registers

NameRegister numberBase offsetClock domainDescription, see
TraceEnable Start/Stop Resource control0x0060x018CLKETM Architecture Specification.
TraceEnable Control 20x0070x01CCLKETM Architecture Specification.
TraceEnable Event0x0080x020CLKETM Architecture Specification.
TraceEnable Control 10x0090x024CLKETM Architecture Specification.
ViewData Event0x00C0x030CLKETM Architecture Specification.
ViewData Control 10x00D0x034CLKETM Architecture Specification.
ViewData Control 30x00F0x03CCLKETM Architecture Specification.

Comparator registers

Table 3.4 shows the Comparator registers. These control the Address, Data and Context ID comparators.

Table 3.4. Comparator registers

NameRegister numberBase offsetClock domainDescription, see
Address Comparator Value 1 - 80x010 to 0x0170x040 to 0x05FCLKETM Architecture Specification.
Address Comparator Access Type 1 - 80x020 to 0x0270x080 to 0x09FCLKETM Architecture Specification.[1]
Data Comparator Value 1 [2]0x030 [2]0x0C0 [2]CLKETM Architecture Specification.
Data Comparator Value 3 [2]0x032 [2]0x0C8 [2]CLKETM Architecture Specification.
Data Comparator Mask 1 [2]0x040 [2]0x100 [2]CLKETM Architecture Specification.
Data Comparator Mask 3 [2]0x042 [2]0x108 [2]CLKETM Architecture Specification.
Context ID Comparator Value0x06C0x1B0CLKETM Architecture Specification.
Context ID Comparator Mask0x06F0x1BCCLKETM Architecture Specification.

[1] Because the Cortex-R4 processor does not implement the Security Extensions, only bits [9:0] of the Address Comparator Access Type Registers are implemented.

[2] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM‑R4, reserved areas are:

   Register 0x031, Data Comparator Value 1, at offset 0x0C4     Register 0x033, Data Comparator Value 3, at offset 0x0CC

   Register 0x041, Data Comparator Mask 1, at offset 0x104      Register 0x043, Data Comparator Mask 3, at offset 0x10C.

You must not write to these reserved register addresses. The value of a reads from these addresses is Unknown.

Counter, Sequencer and other resource registers

Table 3.5 shows the Counter, Sequencer and other resource registers. These control:

  • the two Counters, and associated events

  • the Sequencer, and associated state change events

  • Trigger events

  • EXTOUT (External Output) events

  • Extended External Input selection.

Table 3.5. Counter, Sequencer and other resource registers

NameRegister numberBase offsetClock domainDescription, see
Trigger Event0x0020x008CLKETM Architecture Specification.
Counter Reload Value 1 - 20x050, 0x0510x140, 0x144CLKETM Architecture Specification.
Counter Enable Event 1 - 20x054, 0x0550x150, 0x154CLKETM Architecture Specification.
Counter Reload Event 1 - 20x058, 0x0590x160, 0x164CLKETM Architecture Specification.
Counter Value 1 - 20x05C, 0x05D0x170, 0x174CLKETM Architecture Specification.
Sequencer State Transition Events0x060 to 0x0650x180 to 0x194CLKETM Architecture Specification.
Current Sequencer State0x0670x19CCLKETM Architecture Specification.
External Output Event 1 - 20x068, 0x0690x1A0, 0x1A4CLKETM Architecture Specification.
Extended External Input Selector0x07B0x1ECCLKExtended External Input Selection Register.

CoreSight Management registers

Table 3.6 shows the CoreSight Management registers.

Table 3.6. CoreSight Management registers

NameRegister numberBase offsetClock domainDescription, see
Integration Mode Control0x3C00xF00PCLKDBGETM Architecture Specification
Claim Tag Set0x3E80xFA0PCLKDBGETM Architecture Specification
Claim Tag Clear0x3E90xFA4PCLKDBGETM Architecture Specification
Lock Access0x3EC0xFB0PCLKDBGETM Architecture Specification
Lock Status0x3ED0xFB4PCLKDBGETM Architecture Specification
Authentication Status0x3EE0xFB8PCLKDBGETM Architecture Specification
Device Configuration0x3F20xFC8PCLKDBGETM Architecture Specification
Device Type0x3F30xFCCPCLKDBGETM Architecture Specification
Peripheral ID4 to 70x3F4 to 0x3F70xFD0 to 0xFDCPCLKDBGPeripheral Identification Registers
Peripheral ID0 to 30x3F8 to 0x3FB0xFE0 to 0xFECPCLKDBG
Component ID0 to 30x3FC to 0x3FF0xFF0 to 0xFFCPCLKDBGComponent Identification Registers

Integration Test registers

Table 3.7 shows the Integration Test registers.

Table 3.7. Integration Test registers

NameRegister numberBase offsetClock domainDescription, see
ITETMIF0x3B60xED8CLKITETMIF Register, ETM interface
ITMISCOUT0x3B70xEDCCLKITMISCOUT Register, miscellaneous outputs
ITMISCIN0x3B80xEE0CLKITMISCIN Register, miscellaneous inputs
ITTRIGGERACK0x3B90xEE4ATCLKITTRIGGERACK Register, trigger acknowledge
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