2.8.1. ETMR4 clock signals

ETMR4 contains the following clocks:

CLK

This is the main clock for the ETMR4 block and must be the same clock as that wired to the CLK input of the Cortex‑R4 processor. It can be asynchronous to PCLKDBG and ATCLK.

PCLKDBG

This is the Debug APB interface clock for ETMR4. It can be asynchronous to CLK and ATCLK.

ATCLK

This is the ATB interface clock. It can be asynchronous to CLK and PCLKDBG.

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