3.5.10. Integration Test Registers

The following subsections describe the Integration Test Registers. If you want to access these registers you must first set bit [0] of the Integration Mode Control Register to 1.

See the ETM Architecture Specification for more information. The Integration Mode Control Register is described in the ETM Architecture Specification.

Table 3.17. Output signals that the Integration Test Registers can control

SignalRegisterBitRegister description
AFREADYITATBCTR0[1]See ITATBCTR0 Register, ATB control 0
ATBYTES[1:0]ITATBCTR0[9:8]See ITATBCTR0 Register, ATB control 0
ATDATA[31, 23, 15, 7, 0]ITATBDATA0[4:0]See ITATBDATA0 Register, ATB data 0
ATID[6:0]ITATBCTR1[6:0]See ITATBCTR1 Register, ATB control 1
ATVALIDITATBCTR0[0]See ITATBCTR0 Register, ATB control 0
ETMDBGRQITMISCOUT[4]See ITMISCOUT Register, miscellaneous outputs
EXTOUT[1:0]ITMISCOUT[9:8]See ITMISCOUT Register, miscellaneous outputs
nETMWFIREADYITMISCOUT[5]See ITMISCOUT Register, miscellaneous outputs
TRIGGERITTRIGGERREQ[0]See ITTRIGGERREQ Register, trigger request

Table 3.18. Input signals that the Integration Test Registers can read

SignalRegisterBitRegister description
AFVALIDITATBCTR2[1]See ITATBCTR2 Register, ATB control 2
ATREADYITATBCTR2[0]See ITATBCTR2 Register, ATB control 2
DBGACKITMISCIN[4]See ITMISCIN Register, miscellaneous inputs
ETMCID[31, 0]ITETMIF[11:10]See ITETMIF Register, ETM interface
ETMDA[31, 0]ITETMIF[7:6]See ITETMIF Register, ETM interface
ETMDCTL[11, 0]ITETMIF[5:4]See ITETMIF Register, ETM interface
ETMDD[63, 0]ITETMIF[9:8]See ITETMIF Register, ETM interface
ETMIA[31, 1]ITETMIF[3:2]See ITETMIF Register, ETM interface
ETMICTL[13, 0]ITETMIF[1:0]See ITETMIF Register, ETM interface
ETMWFIPENDINGITMISCIN[5]See ITMISCIN Register, miscellaneous inputs
EVNTBUS[46, 28, 0]ITETMIF[14:12]See ITETMIF Register, ETM interface
EXTIN[3:0]ITMISCIN[3:0]See ITMISCIN Register, miscellaneous inputs
TRIGGERACKITTRIGGERACK[0]See ITTRIGGERACK Register, trigger acknowledge

Using the Integration Test Registers

The CoreSight ETM‑R4 Integration Manual gives a full description of the use of the Integration Test Registers to check integration. In brief:

  • When bit [0] of the Integration Mode Control Register is set to 1, values written to the write-only integration test registers map onto the specified outputs of the macrocell. For example, writing 0x3 to ITMISCOUT[9:8] causes EXTOUT[1:0] to take the value 0x3.

  • When bit [0] of the Integration Mode Control Register is set to 1, values read from the read-only integration test registers correspond to the values of the specified inputs of the macrocell. For example, if you read ITMISCIN[3:0] you obtain the value of EXTIN[3:0].

When bit [0] of the Integration Mode Control Register is set to 0:

  • Reading an Integration Test Register returns an Unpredictable value.

  • The effect of attempting to write to an Integration Test Register, other than the read-only Integration Test Registers, is Unpredictable.

    Note

    You must not attempt to write to an Integration Test Register unless you have set bit [0] of the Integration Mode Control Register to 1.

See the ETM Architecture Specification for details of the Integration Mode Control Register.

ITETMIF Register, ETM interface

The ITETMIF Register, 0x3B6 at offset 0xED8, is read-only. Figure 3.12 shows the assignment of bits in the register.

Figure 3.12. ITETMIF Register bit assignments

Table 3.21 lists how the bit values correspond with the register functions. The value of these fields depend on the signals on the input pins when the register is read.

Table 3.19. ITETMIF Register bit assignments

BitsNameFunction
[31:15]-Reserved. Read undefined.
[14]EVNTBUS[46]Returns the value of the EVNTBUS[46] input pin [1].
[13]EVNTBUS[28]Returns the value of the EVNTBUS[28] input pin [1].
[12]EVNTBUS[0]Returns the value of the EVNTBUS[0] input pin [1].
[11]ETMCID[31]Returns the value of the ETMCID[31] input pin [1].
[10]ETMCID[0]Returns the value of the ETMCID[0] input pin [1].
[9]ETMDD[63]Returns the value of the ETMDD[63] input pin [1].
[8]ETMDD[0]Returns the value of the ETMDD[0] input pin [1].
[7]ETMDA[31]Returns the value of the ETMDA[31] input pin [1].
[6]ETMDA[0]Returns the value of the ETMDA[0] input pin [1].
[5]ETMDCTL[11]Returns the value of the ETMDCTL[11] input pin [1].
[4]ETMDCTL[0]Returns the value of the ETMDCTL[0] input pin [1].
[3]ETMIA[31]Returns the value of the ETMIA[31] input pin [1].
[2]ETMIA[1]Returns the value of the ETMIA[1] input pin [1].
[1]ETMICTL[13]Returns the value of the ETMICTL[13] input pin [1].
[0]ETMICTL[0]Returns the value of the ETMICTL[0] input pin [1].

[1] When a bit is set to 0, the corresponding input pin is LOW.

When a bit is set to 1, the corresponding input pin is HIGH.

The Integration Test Register bits values always correspond to the physical state of the input pins.

ITMISCOUT Register, miscellaneous outputs

The ITMISCOUT Register, register 0x3B7 at offset 0xEDC, is write-only. Figure 3.13 shows the arrangement of bits in the register.

Figure 3.13. ITMISCOUT Register bit assignments

Table 3.20 lists how the bit values correspond with the register functions.

Table 3.20. ITMISCOUT Register bit assignments

BitsNameFunction
[31:10]-Reserved. Write as zero.
[9:8]EXTOUTDrives the EXTOUT[1:0] output pins[1].
[7:6]-Reserved. Write as zero.
[5]ETMWFIREADY

Drives the nETMWFIREADY output pin[1].

[4]ETMDBGRQDrives the ETMDBGRQ output pin[1].
[3:0]-Reserved. Write as zero.

[1] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The Integration Test Register bits values correspond to the physical state of the output pins.

ITMISCIN Register, miscellaneous inputs

The ITMISCIN Register, register 0x3B8 at offset 0xEE0, is read-only. Figure 3.14 shows the arrangement of bits in the register.

Figure 3.14. ITMISCIN Register bit assignments

Table 3.21 lists how the bit values correspond with the register functions. The values of these fields depend on the signals on the input pins when the register is read.

Table 3.21. ITMISCIN Register bit assignments

BitsNameFunction
[31:6]-Reserved. Read undefined.
[5]ETMWFIPENDINGReturns the value of the ETMWFIPENDING input pin[1].
[4]DBGACKReturns the value of the DBGACK input pin[1].
[3:0]EXTINReturns the value of the EXTIN[3:0] input pins[1].

[1] When a bit is set to 0, the corresponding input pin is LOW.

When a bit is set to 1, the corresponding input pin is HIGH.

The Integration Test Register bits values always correspond to the physical state of the input pins.

ITTRIGGERACK Register, trigger acknowledge

The ITTRIGGERACK Register, register 0x3B9 at offset 0xEE4, is read-only. Figure 3.15 shows the arrangement of bits in the register.

Figure 3.15. ITTRIGGERACK Register bit assignments

Table 3.22 lists how the bit values correspond with the register functions. The value of this field depends on the signal on the input pins when the register is read.

Table 3.22. ITTRIGGERACK Register bit assignments

BitsNameFunction
[31:1]-Reserved. Read undefined.
[0]TRIGGERACKReturns the value of the TRIGGERACK input pin[1].

[1] When a bit is set to 0, the corresponding input pin is LOW.

When a bit is set to 1, the corresponding input pin is HIGH.

The Integration Test Register bits values always correspond to the physical state of the input pins.

ITTRIGGERREQ Register, trigger request

The ITTRIGGERREQ Register, register 0x3BA at offset 0xEE8, is write-only. Figure 3.16 shows the arrangement of bits in the register.

Figure 3.16. ITTRIGGERREQ Register bit assignments

Table 3.23 lists how the bit values correspond with the register functions.

Table 3.23. ITTRIGGERREQ Register bit assignments

BitsNameFunction
[31:1]-Reserved. Write as zero.
[0]TRIGGERDrives the TRIGGER output pin[1].

[1] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The Integration Test Register bits values always correspond to the physical state of the output pins.

ITATBDATA0 Register, ATB data 0

The ITATBDATA0 Register, register 0x3BB at offset 0xEEC, is write-only. Figure 3.17 shows the arrangement of bits in the register.

Figure 3.17. ITATBDATA0 Register bit assignments

Table 3.24 lists how the bit values correspond with the register functions.

Table 3.24. ITATBDATA0 Register bit assignments

BitsNameFunction
[31:5]-Reserved. Write as zero.
[4:0]ATDATADrives the ATDATA[31, 23, 15, 7, 0] output pins[1].

[1] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The Integration Test Register bits values always correspond to the physical state of the output pins.

ITATBCTR2 Register, ATB control 2

The ITATBCTR2 Register, register 0x3BC at offset 0xEF0, is read-only. Figure 3.18 shows the arrangement of bits in the register.

Figure 3.18. ITATBCTR2 Register bit assignments

Table 3.25 lists how the bit values correspond with the register functions. The values of these fields depend on the signals on the input pins when the register is read.

Table 3.25. ITATBCTR2 Register bit assignments

BitsNameFunction
[31:2]-Reserved. Read undefined.
[1]AFVALIDReturns the value of the AFVALID input pin[1].
[0]ATREADYReturns the value of the ATREADY input pin[1].

[1] When a bit is set to 0, the corresponding input pin is LOW.

When a bit is set to 1, the corresponding input pin is HIGH.

The Integration Test Register bits values always correspond to the physical state of the input pins.

ITATBCTR1 Register, ATB control 1

The ITATBCTR1 Register, register 0x3BD at offset 0xEF4, is write-only. Figure 3.19 shows the arrangement of bits in the register.

Figure 3.19. ITATBCTR1 Register bit assignments

Table 3.26 lists how the bit values correspond with the register functions.

Table 3.26. ITATBCTR1 Register bit assignments

BitsNameFunction
[31:7]-Reserved. Write as zero.
[6:0]ATIDDrives the ATID[6:0] output pins[1].

[1] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The Integration Test Register bits values always correspond to the physical state of the output pins.

ITATBCTR0 Register, ATB control 0

The ITATBCTR0 Register, register 0x3BE at offset 0xEF8, is write-only. Figure 3.20 shows the arrangement of bits in the register.

Figure 3.20. ITATBCTR0 Register bit assignments

Table 3.27 lists how the bit values correspond with the register functions.

Table 3.27. ITATBCTR0 Register bit assignments

BitsNameFunction
[31:10]-Reserved. Write as zero.
[9:8]ATBYTESDrives the ATBYTES[1:0] output pins[1].
[7:2]-Reserved. Write as zero.
[1]AFREADYDrives the AFREADY output pin[1].
[0]ATVALIDDrives the ATVALID output pin[1].

[1] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The Integration Test Register bits values always correspond to the physical state of the output pins.

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