C.3. APB operating states

Figure C.5 shows the operational activity of the APB.

The state machine operates through the following states:


This is the default state of the APB.


When a transfer is required the bus moves into the SETUP state, where the appropriate select signal, PSELx, is asserted. The bus only remains in the SETUP state for one clock cycle and always moves to the ACCESS state on the next rising edge of the clock.


The enable signal, PENABLE, is asserted in the ACCESS state. The address, write, and select signals all remain stable during the transition from the SETUP to ACCESS state. The PREADY signal from the slave controls the exit from the ACCESS state:

  • If PREADY is held LOW by the slave then the peripheral bus remains in the ACCESS state.

  • If PREADY is driven HIGH by the slave then the ACCESS state is exited and the bus returns to the IDLE state if no more transfers are required. Alternatively, the bus moves directly to the SETUP state if another transfer follows.

Figure C.5. Debug APB state diagram

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