B.1. ETM-R4 input and output signal timing parameters

Signals are classified according to the percentage of the clock period taken up by internal logic.

The timing classifications used are based on these delays:

Early

The delay is less than 20% of the period.

Middle

The delay is between 20% and 80% of the period.

Late

The delay is greater than 80% of the period.

Table B.1 describes the ETM-R4 signal timing parameters.

Table B.1. ETM-R4 signal timing parameters

Signal nameTiming classificationInput/Output
AFREADYMiddleOutput
AFVALIDMiddleInput
ASICCTL[7:0]MiddleOutput
ATBYTES[1:0]MiddleOutput
ATCLK-Input
ATCLKENMiddleInput
ATDATA[31:0]MiddleOutput
ATID[6:0]MiddleOutput
ATREADYMiddleInput
ATVALIDMiddleOutput
CLK-Input
CORESELECT[2:0]MiddleOutput
DBGACKMiddleInput
DBGENMiddleInput

ETMCID[31:0]

MiddleInput
ETMDA[31:0]MiddleInput
ETMDBGRQMiddleOutput
ETMDD[63:0]MiddleInput
ETMDCTL[11:0]MiddleInput
ETMENMiddleOutput
ETMIA[31:1]MiddleInput
ETMICTL[13:0]MiddleInput
ETMPWRUPMiddleOutput
ETMWFIPENDINGMiddleInput
EVNTBUS[46:0]MiddleInput
EXTIN[3:0]MiddleInput
EXTOUT[1:0]MiddleOutput
FIFOPEEK[6:0]MiddleOutput
MAXCORES[2:0]MiddleInput
MAXEXTIN[2:0]MiddleInput
MAXEXTOUT[1:0]MiddleInput
nETMWFIREADYMiddleOutput
NIDENMiddleInput
PADDRDBG[11:2]MiddleInput
PADDRDBG31MiddleInput
PCLKDBGMiddleInput
PCLKENDBGMiddleInput
PENABLEDBGMiddleInput
PRDATADBG[31:0]MiddleOutput
PREADYDBGLateOutput
PRESETDBGnLateInput
PSELDBGMiddleInput
PWDATADBG[31:0]MiddleInput
PWRITEDBGMiddleInput
RSTBYPASSMiddleInput
SEMiddleInput
nSYSPORESETMiddleInput
TRIGGERMiddleOutput
TRIGGERACKMiddleInput
TRIGSBYPASSMiddleInput

Note

Actual clock frequencies and input and output timing constraints vary according to application requirements and the silicon process technologies used. The maximum operating clock frequencies change according to the constraints and the process technology you use.

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