3.5.2. Configuration Code Register

The ETMCCR characteristics are:


Indicates the configuration of the ETM-R4 macrocell.

Usage constraints

There are no usage constraints.


Always available.


See the register summary in Table 3.1 and Table 3.2.

If the MAXEXTOUT[1:0] and MAXEXTIN[2:0] signals are all tied LOW (0) the ETMCCR has the value 0x8D014024.

Figure 3.3 shows the ETMCCR bit assignments.

Figure 3.3. ETMCCR bit assignments

Table 3.9 lists the ETMCCR bit assignments

Table 3.9. ETMCCR bit assignments

[31]1ETMIDR present.
[30:28]b000Reserved. Read-As-Zero (RAZ).
[27]1Software access is supported.
[26]1Trace start/stop block is present.
[25:24]b01Number of Context ID comparators.
[23]0FIFOFULL logic absent.

Reserved, Read-As-Zero.

The Embedded Trace Macrocell Architecture Specification defines this as the most significant bit of the Number of external outputs field, see the description of bits[21:20].


Number of external outputs. Determined by the MAXEXTOUT[1:0] inputs.

The maximum value of this field is 2, because CoreSight ETM‑R4 supports a maximum of 2 external outputs.


Number of external inputs. Determined by the MAXEXTIN[2:0] inputs.

The maximum value of this field is 4, because CoreSight ETM‑R4 supports a maximum of 4 external inputs.

[16]1The sequencer is present.
[15:13]2Number of counters.
[12:8]0Number of memory map decoders.
[7:4]2Number of data comparators.
[3:0]4Number of pairs of address comparators.

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