1.3. Features

ETM-R4 supports tracing of 32-bit ARM instructions, and 16-bit and 32-bit Thumb instructions.

See the Embedded Trace Macrocell Architecture Specification for information about:

Table 1.1 lists the features of the ETM-R4 that are implementation-defined, in terms of either:

Table 1.1. ETM-R4 features with implementation-defined number of instances or size

FeatureETM-R4 valueNotes
Address comparators4 pairsSee bits[3:0] of the ETMCCR [a]
Data value comparators2See bits[7:4] of the ETMCCR [a]
EmbeddedICE watchpoint comparatorsNot implementedNot supported in ETMv3.3
Context ID comparators1See bits[25:24] of the ETMCCR [a]
Counters2See bits[15:13] of the ETMCCR [a]
Sequencer1See bit[16] of the ETMCCR. [a]
Memory Map decoder inputsNot implementedSee bits[12:8] of the ETMCCR [a]
External inputs0-4See bits[19:17] of the ETMCCR [a]
External outputs0-2See bits[22:20] of the ETMCCR [a]
Extended external input bus width47See bits[10:3] of the ETMCCER [b]
Extended external input selectors2See bits[2:0] of the ETMCCER [b]
Instrumentation resourcesNot implementedNot supported in ETMv3.3
Trace port size32-bitSee bits[21,6:4] of the ETMCR [c]
FIFO size144 bytes-
ASICCTL general-purpose bus interface8-bitSee ETMASICCR[d]

Table 1.2 lists which optional features of the ETM architecture the ETM-R4 implements.

Table 1.2. ETM-R4 implementation of optional features

FIFOFULL controlNoSee bit[23] of the ETMCCR [a]
Trace Start/Stop blockYesSee bit[26] of the ETMCCR [a]
Trace all branchesYesSee bit[8] of the ETMCR [b]
Cycle-accurate traceYesSee bit[12] of the ETMCR [b]
Data trace options
 Data address tracingYesSee bits[3:2] of the ETMCR [b]
 Data value tracingYesSee bits[3:2] of the ETMCR [b]
 Data-only tracingYesSee bit[20] of the ETMCR [b]
 CPRT tracingYesSee bits[19, 1] of the ETMCR [b]
Data address comparisonYesBit[12] of the ETMCCER [c] reads-as-zero
EmbeddedICE behavior controlNoNot supported in ETMv3.3
EmbeddedICE inputs to Trace Start/Stop blockNoNot supported in ETMv3.3
Alternative address compressionNoNot supported in ETMv3.3
OS Lock mechanismNoNot implemented
Secure non-invasive debugNoCortex-R4 does not implement the Security Extensions
Context ID tracingYesSee bits[15:14] of the ETMCR [b]
Trace outputYesATB

See Appendix A Signal Descriptions for information about the macrocell signals.

Copyright © 2005, 2007-2009 ARM Limited. All rights reserved.ARM DDI 0367C