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ETM-R4 supports tracing of 32-bit ARM instructions, and 16-bit and 32-bit Thumb instructions.
See the Embedded Trace Macrocell Architecture Specification for information about:
the trace protocol
the features of ETMv3.3
controlling tracing using triggering and filtering resources
ETM sharing.
Table 1.1 lists the features of the ETM-R4 that are implementation-defined, in terms of either:
the number of times the feature is implemented
the size of the feature.
Table 1.1. ETM-R4 features with implementation-defined number of instances or size
Feature | ETM-R4 value | Notes |
---|---|---|
Address comparators | 4 pairs | See bits[3:0] of the ETMCCR [a] |
Data value comparators | 2 | See bits[7:4] of the ETMCCR [a] |
EmbeddedICE watchpoint comparators | Not implemented | Not supported in ETMv3.3 |
Context ID comparators | 1 | See bits[25:24] of the ETMCCR [a] |
Counters | 2 | See bits[15:13] of the ETMCCR [a] |
Sequencer | 1 | See bit[16] of the ETMCCR. [a] |
Memory Map decoder inputs | Not implemented | See bits[12:8] of the ETMCCR [a] |
External inputs | 0-4 | See bits[19:17] of the ETMCCR [a] |
External outputs | 0-2 | See bits[22:20] of the ETMCCR [a] |
Extended external input bus width | 47 | See bits[10:3] of the ETMCCER [b] |
Extended external input selectors | 2 | See bits[2:0] of the ETMCCER [b] |
Instrumentation resources | Not implemented | Not supported in ETMv3.3 |
Trace port size | 32-bit | See bits[21,6:4] of the ETMCR [c] |
FIFO size | 144 bytes | - |
ASICCTL general-purpose bus interface | 8-bit | See ETMASICCR[d] |
[a] See Configuration Code Register. [c] See ETM Main Control Register. [d] See ASIC Control Register |
Table 1.2 lists which optional features of the ETM architecture the ETM-R4 implements.
Table 1.2. ETM-R4 implementation of optional features
Feature | Implemented? | Notes | |
---|---|---|---|
FIFOFULL control | No | See bit[23] of the ETMCCR [a] | |
Trace Start/Stop block | Yes | See bit[26] of the ETMCCR [a] | |
Trace all branches | Yes | See bit[8] of the ETMCR [b] | |
Cycle-accurate trace | Yes | See bit[12] of the ETMCR [b] | |
Data trace options | |||
Data address tracing | Yes | See bits[3:2] of the ETMCR [b] | |
Data value tracing | Yes | See bits[3:2] of the ETMCR [b] | |
Data-only tracing | Yes | See bit[20] of the ETMCR [b] | |
CPRT tracing | Yes | See bits[19, 1] of the ETMCR [b] | |
Data address comparison | Yes | Bit[12] of the ETMCCER [c] reads-as-zero | |
EmbeddedICE behavior control | No | Not supported in ETMv3.3 | |
EmbeddedICE inputs to Trace Start/Stop block | No | Not supported in ETMv3.3 | |
Alternative address compression | No | Not supported in ETMv3.3 | |
OS Lock mechanism | No | Not implemented | |
Secure non-invasive debug | No | Cortex-R4 does not implement the Security Extensions | |
Context ID tracing | Yes | See bits[15:14] of the ETMCR [b] | |
Trace output | Yes | ATB | |
[a] See Configuration Code Register. [b] See ETM Main Control Register. |
See Appendix A Signal Descriptions for information about the macrocell signals.