3.4.1. Functional grouping of registers

This section lists the macrocell registers by functional group, as follows:

These functional groups include all of the registers.

General control and ID registers

Table 3.2 lists the general control and ID registers in register number order.

Table 3.2. General control and ID registers

Register numberNameBase offsetClock domainDescription
0x000ETM Control0x000CLKETM Main Control Register
0x001Configuration Code0x004CLKConfiguration Code Register
0x003ASIC Control0x00CCLKASIC Control Register
0x004ETM Status0x010CLKEmbedded Trace Macrocell Architecture Specification.
0x005System Configuration0x014CLKEmbedded Trace Macrocell Architecture Specification.
0x00BFIFOFULL Level[a]0x02CCLKEmbedded Trace Macrocell Architecture Specification.
0x078Synchronization Frequency0x1E0CLKEmbedded Trace Macrocell Architecture Specification.[b]
0x079ETM ID0x1E4CLKETM ID Register
0x07AConfiguration Code Extension0x1E8CLKConfiguration Code Extension Register
0x080CoreSight Trace ID0x200CLKEmbedded Trace Macrocell Architecture Specification.
0x0C5Power-Down Status 0x314CLKPower-Down Status Register

[a] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the Embedded Trace Macrocell Architecture Specification.

[b] Only bits[11:2] of the Synchronization Frequency Register are implemented. Bits[1:0] Read-As-Zero.


TraceEnable and ViewData registers

Table 3.3 lists the TraceEnable and ViewData registers in register number order.

Table 3.3. TraceEnable and ViewData registers

Register numberNameBase offsetClock domainDescription
0x006TraceEnable Start/Stop Resource control0x018CLKEmbedded Trace Macrocell Architecture Specification.
0x007TraceEnable Control 20x01CCLKEmbedded Trace Macrocell Architecture Specification.
0x008TraceEnable Event0x020CLKEmbedded Trace Macrocell Architecture Specification.
0x009TraceEnable Control 10x024CLKEmbedded Trace Macrocell Architecture Specification.
0x00CViewData Event0x030CLKEmbedded Trace Macrocell Architecture Specification.
0x00DViewData Control 10x034CLKEmbedded Trace Macrocell Architecture Specification.
0x00FViewData Control 30x03CCLKEmbedded Trace Macrocell Architecture Specification.

Comparator registers

Table 3.4 lists the Comparator registers in register number order. These control the Address, Data and Context ID comparators.

Table 3.4. Comparator registers

Register numberNameBase offsetClock domainDescription
0x010 to 0x017Address Comparator Value 1 - 80x040 to 0x05FCLKEmbedded Trace Macrocell Architecture Specification
0x020 to 0x027Address Comparator Access Type 1 - 80x080 to 0x09FCLKEmbedded Trace Macrocell Architecture Specification[a]
0x030 [b]Data Comparator Value 1 [b]0x0C0 [b]CLKEmbedded Trace Macrocell Architecture Specification
0x032 [b]Data Comparator Value 3 [b]0x0C8 [b]CLKEmbedded Trace Macrocell Architecture Specification
0x040 [b]Data Comparator Mask 1 [b]0x100 [b]CLKEmbedded Trace Macrocell Architecture Specification
0x042 [b]Data Comparator Mask 3 [b]0x108 [b]CLKEmbedded Trace Macrocell Architecture Specification
0x06CContext ID Comparator Value0x1B0CLKEmbedded Trace Macrocell Architecture Specification
0x06FContext ID Comparator Mask0x1BCCLKEmbedded Trace Macrocell Architecture Specification

[a] Because the Cortex-R4 processor does not implement the Security Extensions, only bits[9:0] of the Address Comparator Access Type Registers are implemented.

[b] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM‑R4, reserved areas are:

    Register 0x031, Data Comparator Value 1, at offset 0x0C4     Register 0x033, Data Comparator Value 3, at offset 0x0CC

    Register 0x041, Data Comparator Mask 1, at offset 0x104      Register 0x043, Data Comparator Mask 3, at offset 0x10C.

You must not write to these reserved register addresses. The value of a reads from these addresses is Unknown.


Counter, Sequencer and other resource registers

Table 3.5 lists the Counter, Sequencer and other resource registers in register number order. These control:

  • the two Counters, and associated events

  • the Sequencer, and associated state change events

  • Trigger events

  • EXTOUT (External Output) events

  • Extended External Input selection.

Table 3.5. Counter, Sequencer and other resource registers

Register numberNameBase offsetClock domainDescription
0x002Trigger Event0x008CLKEmbedded Trace Macrocell Architecture Specification.
0x050, 0x051Counter Reload Value 1 - 20x140, 0x144CLKEmbedded Trace Macrocell Architecture Specification.
0x054, 0x055Counter Enable Event 1 - 20x150, 0x154CLKEmbedded Trace Macrocell Architecture Specification.
0x058, 0x059Counter Reload Event 1 - 20x160, 0x164CLKEmbedded Trace Macrocell Architecture Specification.
0x05C, 0x05DCounter Value 1 - 20x170, 0x174CLKEmbedded Trace Macrocell Architecture Specification.
0x060 to 0x065Sequencer State Transition Events0x180 to 0x194CLKEmbedded Trace Macrocell Architecture Specification.
0x067Current Sequencer State0x19CCLKEmbedded Trace Macrocell Architecture Specification.
0x068, 0x069External Output Event 1 - 20x1A0, 0x1A4CLKEmbedded Trace Macrocell Architecture Specification.
0x07BExtended External Input Selector0x1ECCLKExtended External Input Selection Register.

CoreSight Management registers

Table 3.6 lists the CoreSight Management registers in register number order.

Table 3.6. CoreSight Management registers

Register numberNameBase offsetClock domainDescription
0x3C0Integration Mode Control0xF00PCLKDBGEmbedded Trace Macrocell Architecture Specification
0x3E8Claim Tag Set0xFA0PCLKDBGEmbedded Trace Macrocell Architecture Specification
0x3E9Claim Tag Clear0xFA4PCLKDBGEmbedded Trace Macrocell Architecture Specification
0x3ECLock Access0xFB0PCLKDBGEmbedded Trace Macrocell Architecture Specification
0x3EDLock Status0xFB4PCLKDBGEmbedded Trace Macrocell Architecture Specification
0x3EEAuthentication Status0xFB8PCLKDBGEmbedded Trace Macrocell Architecture Specification
0x3F2Device Configuration0xFC8PCLKDBGEmbedded Trace Macrocell Architecture Specification
0x3F3Device Type0xFCCPCLKDBGEmbedded Trace Macrocell Architecture Specification
0x3F4 to 0x3F7Peripheral ID4 to 70xFD0 to 0xFDCPCLKDBGPeripheral Identification Registers
0x3F8 to 0x3FBPeripheral ID0 to 30xFE0 to 0xFECPCLKDBG
0x3FC to 0x3FFComponent ID0 to 30xFF0 to 0xFFCPCLKDBGComponent Identification Registers

Integration Test registers

Table 3.7 lists the Integration Test registers in register number order.

Table 3.7. Integration Test registers

Register numberNameBase offsetClock domainDescription
0x3B6ITETMIF0xED8CLKProcessor-ETM Interface Register
0x3B7ITMISCOUT0xEDCCLKMiscellaneous Outputs Register
0x3B8ITMISCIN0xEE0CLKMiscellaneous Inputs Register
0x3B9ITTRIGGERACK0xEE4ATCLKTrigger Acknowledge Register
0x3BAITTRIGGERREQ0xEE8ATCLKTrigger Request Register
0x3BBITATBDATA00xEECATCLKATB Data Register 0
0x3BCITATBCTR20xEF0ATCLKATB Control Register 2
0x3BDITATBCTR10xEF4ATCLKATB Control Register 1
0x3BEITATBCTR00xEF8ATCLKATB Control Register 0

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