3.4. Register summary

This section summarizes the ETM registers. For full descriptions of the ETM registers, see:

Table 3.1 lists all of the registers, and tells you where each register is described in detail. The registers are listed in register number order.

The macrocell registers are listed by functional group in the section Functional grouping of registers. The functional group register tables include additional information about each register:

Note

  • Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.

  • In Table 3.1:

    • The Default value column shows the value of the register immediately after an ETM reset. For read-only registers, every read of the register returns this value.

    • The listed Functional group table gives more information about the register, including its clock domain.

    • Access type is described as follows:

      RW

      Read and write

      RO

      Read only

      WO

      Write only.

All ETM registers are 32-bits wide.

Table 3.1. ETM-R4 register summary

Register numberNameTypeResetGroup [a]Description
0x000ETMCRRW0x000004411ETM Main Control Register
0x001ETMCCRRO0x8D014024 [b]1Configuration Code Register
0x002ETMTRIGGERRW- [c]4Trigger Event Register in the Embedded Trace Macrocell Architecture Specification
0x003ETMASICCTLRRW0x000000001ASIC Control Register
0x004ETMSR,RW- [c]1ETM Status Register in the Embedded Trace Macrocell Architecture Specification
0x005ETMSCRRO0x00020C0C [d]1System Configuration Register in the Embedded Trace Macrocell Architecture Specification
0x006ETMTSSCRRW- [c]2TraceEnable Start/Stop Control Register in the Embedded Trace Macrocell Architecture Specification
0x007ETMTECR2RW- [c]2TraceEnable Control 2 Register in the Embedded Trace Macrocell Architecture Specification
0x008ETMTEEVRRW- [c]2TraceEnable Event Register in the Embedded Trace Macrocell Architecture Specification
0x009ETMTECR1RW- [c]2TraceEnable Control 1 Register in the Embedded Trace Macrocell Architecture Specification
0x00BETMFFLR[e]RW- [c]1FIFOFULL Level Register in the Embedded Trace Macrocell Architecture Specification
0x00CETMVDEVRRW- [c]2ViewData Event Register in the Embedded Trace Macrocell Architecture Specification
0x00DETMVDCR1RW- [c]2ViewData Control 1 Register in the Embedded Trace Macrocell Architecture Specification
0x00FETMVDCR3RW- [c]2ViewData Control 3 Register in the Embedded Trace Macrocell Architecture Specification
0x010 to 0x017ETMACVR1-8RW- [c]3Address Comparator Value Registers in the Embedded Trace Macrocell Architecture Specification
0x020 to 0x027ETMACTR1-8RW- [c]3Address Comparator Access Type Registers in the Embedded Trace Macrocell Architecture Specification
0x030[f]ETMDCVR1[f]RW- [c]3Data Comparator Value Registers in the Embedded Trace Macrocell Architecture Specification
0x032[f]ETMDCVR3[f]RW- [c]3Data Comparator Value Registers in the Embedded Trace Macrocell Architecture Specification
0x040[f]ETMDCMR1[f]RW- [c]3Data Comparator Mask Registers in the Embedded Trace Macrocell Architecture Specification
0x042[f]ETMDCMR3[f]RW- [c]3Data Comparator Mask Registers in the Embedded Trace Macrocell Architecture Specification
0x050, 0x051ETMCNTRLDVR1-2RW- [c]4Counter Reload Value Registers in the Embedded Trace Macrocell Architecture Specification
0x054, 0x055ETMCNTENR1-2RW- [c]4Counter Enable Registers in the Embedded Trace Macrocell Architecture Specification
0x058, 0x059ETMCNTRLDEVR1-2RW- [c]4Counter Reload Event Registers in the Embedded Trace Macrocell Architecture Specification
0x05C, 0x05DETMCNTVR1-2RW- [c]4Counter Value Registers in the Embedded Trace Macrocell Architecture Specification
0x060 to 0x065ETMSQEVRRW- [c]4Sequencer State Transition Event Registers in the Embedded Trace Macrocell Architecture Specification
0x067ETMSQRRW- [c]4Current Sequencer State Register in the Embedded Trace Macrocell Architecture Specification
0x068, 0x069ETMEXTOUTEVR1-2RW- [c]4External Output Event Registers in the Embedded Trace Macrocell Architecture Specification
0x06CETMCIDCVRRW- [c]3Context ID Comparator Value Registers in the Embedded Trace Macrocell Architecture Specification
0x06FETMCIDCMRRW- [c]3Context ID Comparator Mask Register in the Embedded Trace Macrocell Architecture Specification
0x078ETMSYNCFRRW0x000004001Synchronization Frequency Register in the Embedded Trace Macrocell Architecture Specification
0x079ETMIDRRO0x4104F23x [g]1ETM ID Register
0x07AETMCCERRO0x0000097A1Configuration Code Extension Register
0x07BETMEXTINSELRRW- [c]4Extended External Input Selection Register
0x080ETMTRACEIDRRW0x000000001CoreSight Trace ID Register in the Embedded Trace Macrocell Architecture Specification
0x0C5ETMPDSRRO- [c]1Power-Down Status Register
0x3B6ITETMIFRO [h]-[i]6Processor-ETM Interface Register
0x3B7ITMISCOUTWOn/a [j]6Miscellaneous Outputs Register
0x3B8ITMISCINRO [h]- [i]6Miscellaneous Inputs Register
0x3B9ITTRIGGERACKRO [h]- [i]6Trigger Acknowledge Register
0x3BAITTRIGGERREQWOn/a [j]6Trigger Request Register
0x3BBITATBDATA0WOn/a [j]6ATB Data Register 0
0x3BCITATBCTR2RO [h]- [i]6ATB Control Register 2
0x3BDITATBCTR1WOn/a [j]6ATB Control Register 1
0x3BEITATBCTR0WOn/a [j]6ATB Control Register 0
0x3C0ETMITCTRLRW0x000000005Integration Mode Control Register in the Embedded Trace Macrocell Architecture Specification
0x3E8ETMCLAIMSETRW0x000000FF5Claim Tag Set Register in the Embedded Trace Macrocell Architecture Specification
0x3E9ETMCLAIMCLRRW0x000000005Claim Tag Clear Register in the Embedded Trace Macrocell Architecture Specification
0x3ECETMLARWOn/a [j]5Lock Access Register in the Embedded Trace Macrocell Architecture Specification
0x3EDETMLSRRO- [i]5Lock Status Register in the Embedded Trace Macrocell Architecture Specification
0x3EEETMAUTHSTATUSRO- [i]5Authentication Status Register in the Embedded Trace Macrocell Architecture Specification
0x3F2ETMDEVIDRO0x000000005CoreSight Device Configuration Register in the Embedded Trace Macrocell Architecture Specification
0x3F3ETMDEVTYPERO0x000000135CoreSight Device Type Register in the Embedded Trace Macrocell Architecture Specification
0x3F4 to 0x3F7ETMPIDR4-7RO- [i]5Peripheral Identification Registers
0x3F8 to 0x3FBEETMPIDR0-3RO- [i]--
0x3FC to 0x3FFETMCIDR0-3RO- [i]5Component Identification Registers

[a] Functional group. For more information, see:

        for Group 1, Table 3.2, Table 3.2

        for Group 2, Table 3.3, Table 3.3

        for Group 3, Table 3.4, Table 3.4

        for Group 4, Table 3.5, Table 3.5

        for Group 5, Table 3.6, Table 3.6

        for Group 6, Table 3.7, Table 3.7.

[b] Default value when MAXEXTOUT[1:0] and MAXEXTIN[2:0] are all tied LOW (0), see the register description for more information.

[c] The register is not reset by a reset of the macrocell. Therefore, it does not have a specific default value, and its reset value is Unknown.

[d] Bits[14:12] of the System Configuration Register are tied to the MAXCORES[2:0] signals. If a MAXCORES bit is High then the corresponding bit in the System Configuration Register is set to 1, for example if MAXCORES[0] is tied HIGH then bit[12] is set to 1. The default value given is for all MAXCORES signals tied LOW, bits[14:12] = b000.

For more information about the MAXCORES[2:0] signals, see ETM-R4 Signals.

[e] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the Embedded Trace Macrocell Architecture Specification.

[f] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM‑R4, reserved areas are:

   Register 0x031, Data Comparator Value 1, at offset 0x0C4     Register 0x033, Data Comparator Value 3, at offset 0x0CC

   Register 0x041, Data Comparator Mask 1, at offset 0x104     Register 0x043, Data Comparator Mask 3, at offset 0x10C.

You must not write to these reserved register addresses. Reads from these addresses are Unpredictable.

[g] The value of bits[3:0] of the ETMIDR depend on the macrocell revision, see ETM ID Register for more information.

[h] The values of the read-only Integration Test registers are valid only when the macrocell is in Integration Test mode. If you read one of these registers when the macrocell is in normal operating mode the result returned is Unknown.

[i] See the register description for details.

[j] Not applicable. These are write-only registers.


Copyright © 2005, 2007-2009 ARM Limited. All rights reserved.ARM DDI 0367C
Non-Confidential