A.6. Miscellaneous interface

Table A.7 lists the ETM sharing signals. Clock domains, where specified, give the clock on which input signals must be generated and output signals sampled. See the CoreSight ETM‑R4 Integration Manual for information about signals and connectivity.

Table A.7. Miscellaneous signals

SignalDirectionDescriptionClock domain
CORESELECT[2:0]Output

Where an ETM is shared between multiple cores, this signal specifies which core to trace.

The value appears as bits[14:12] of the System Configuration Register.

CLK
MAXCORES[2:0]Input

Where an ETM is shared between multiple cores, this signal specifies the number of cores the ETM can trace. It must be tied to the number of cores sharing the ETM minus 1.

These signals determine the value of bits[14:12] of the System Configuration register, see the footnote to Table 3.1.

CLK
ASICCTL[7:0]OutputGeneral purpose outputs controlled by the ETMASICCR. See ASIC Control RegisterCLK
DBGENInput

Invasive debug enable.

When HIGH (1), indicates that invasive debug is enabled.

-
NIDENInput

Non-invasive debug enable.

When HIGH (1), indicates that non-invasive debug is enabled.

-
EXTIN[3:0]InputExternal input resources.CLK
EXTOUT[1:0]OutputExternal outputs.CLK
MAXEXTIN[2:0]Input

Number of external inputs supported by the ASIC (maximum 4).

These signals determine the value bits[19:17] in the ETMCCR, see Configuration Code Register.

CLK
MAXEXTOUT[1:0]Input

Number of external outputs supported by the ASIC (maximum 2).

These signals determine the value bits[22:20] in the ETMCCR, see Configuration Code Register.

CLK
FIFOPEEK[6:0]Output

For validation purposes only.

Indicates when various events occur before being written to the FIFO.

CLK

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