A.2. Clocks and resets

Table A.2 lists the clock and reset signals. Clock domains, where specified, give the clock on which input signals must be generated and output signals sampled. See the CoreSight ETM‑R4 Integration Manual for information about signals and connectivity.

Table A.2. Clock and reset signals

SignalDirectionDescriptionClock domain
CLKInputThis is the main clock for the ETM-R4.-
ATCLKInputATB interface clock.-
ATCLKENInputEnable signal for ATCLK. ATCLK
PCLKDBGInputDebug APB clock.-
PCLKENDBGInputDebug APB clock enable.PCLKDBG

Debug APB interface reset.

Resets all registers.

Internally synchronized

Power-on (main) reset.

Resets all registers.

Internally synchronized

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