A.3. Processor trace interface

Table A.3 lists the trace interface signals from the Cortex-R4. Clock domains, where specified, give the clock on which input signals must be generated and output signals sampled. See the CoreSight ETM‑R4 Integration Manual for information about signals and connectivity.

Table A.3. Processor trace interface signals

SignalDirectionDescriptionClock domain
ETMICTL[13:0]InputInstruction control signals.CLK
ETMIA[31:1]InputAddress for executed instruction.CLK
ETMDCTL[11:0]InputData control signals.CLK
ETMDA[31:0]InputAddress for data transfer.CLK
ETMDD[63:0]InputContains the data value for a Load, Store, MRC, or MCR instruction.CLK

Current value of the processor Context ID Register.

EVNTBUS[46:0]InputGives the status of the performance monitoring events. Used as extended external inputs.CLK
ETMWFIPENDINGInputIndicates that the Cortex‑R4 processor is about to go into Standby mode, and that the ETM must drain its FIFO.CLK
nETMWFIREADYOutputIndicates that the macrocell FIFO is empty and that the Cortex‑R4 processor can be put into Standby mode.CLK
ETMDBGRQOutputRequest from the macrocell for the core to enter debug state. This must be ORed with any ASIC-level DBGRQ signals before being connected to the core EDBGRQ input.CLK

Indicates that the core is in debug state.

This signal is connected to the core general purpose DBGACK output, so that it can be used to determine when ETMDBGRQ can be deasserted. It is also used for other purposes in the ETM, and care must be taken to ensure the timing of this signal is appropriate because it does not come through the main interface between the core and the ETM.


When HIGH, indicates that the macrocell is in use.

When LOW:

  • external logic supporting the macrocell can be clock-gated to conserve power

  • the Cortex‑R4 processor disables the interface

  • logic within the macrocell is clock-gated to conserve power.


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