A.4. APB interface

Table A.4 lists the APB signals. Clock domains, where specified, give the clock on which input signals must be generated and output signals sampled. See the CoreSight ETM‑R4 Integration Manual for information about signals and connectivity.

Table A.4. APB signals

SignalDirectionDescriptionClock domain
PADDRDBG[11:2]InputDebug APB Address Bus.PCLKDBG

Originates as an output signal from the Debug Access Port (DAP):

  • PADDRDBG31 at logic 1 indicates an access from hardware (JTAG)

  • PADDRDBG31 at logic 0 indicates an access from software.

PENABLEDBGInputThe Debug APB interface is enabled for a transfer.PCLKDBG
PSELDBGInputDebug APB slave select signal.PCLKDBG
PREADYDBGOutputUsed to extend Debug APB transfers.PCLKDBG
PRDATADBG[31:0]OutputDebug APB read data.PCLKDBG
PWDATADBG[31:0]InputDebug APB write data.PCLKDBG
PWRITEDBGInputDebug APB transfer direction: 0 = Read 1 = Write.PCLKDBG

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