2.4.3. Parallel instruction execution

The Cortex‑R4 processor supports parallel instruction execution. This means the macrocell is capable of tracing two instructions per cycle.

Although the trace start/stop block is evaluated for each instruction as required, the macrocell cannot trace one instruction without the other. In other words, if one instruction is traced, the instruction it is paired with is always traced as well. If ViewData is active, any data associated with the paired instruction is also traced.

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