2.3.1. ETM-R4 clock signals

ETM-R4 has the following clocks:

CLK

This is the main clock for the ETM-R4 block and must be the same clock as that wired to the CLK input of the Cortex‑R4 processor. It can be asynchronous to PCLKDBG and ATCLK.

PCLKDBG

This is the Debug APB interface clock for ETM-R4. It can be asynchronous to CLK. The CoreSight Technology System Design Guide requires PCLKDBG and ATCLK to be synchronous.

ATCLK

This is the ATB interface clock. It can be asynchronous to CLK. The CoreSight Technology System Design Guide requires PCLKDBG and ATCLK to be synchronous.

Figure 2.1 shows these clock domains.

Note

Typically, in a SoC, you drive PCLKDBG at half the frequency of ATCLK.

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