3.5.10. Integration Test Registers

The following subsections describe the Integration Test Registers. To access these registers you must first set bit[0] of the Integration Mode Control Register (ETMITCTRL) to 1.

See the Embedded Trace Macrocell Architecture Specification for more information. ETMITCTRL is described in the Embedded Trace Macrocell Architecture Specification.

Table 3.17. Output signals that the Integration Test Registers can control

SignalRegisterBitRegister description
AFREADYITATBCTR0[1]See ATB Control Register 0
ATBYTES[1:0]ITATBCTR0[9:8]See ATB Control Register 0
ATDATA[31, 23, 15, 7, 0]ITATBDATA0[4:0]See ATB Data Register 0
ATID[6:0]ITATBCTR1[6:0]See ATB Control Register 1
ATVALIDITATBCTR0[0]See ATB Control Register 0
ETMDBGRQITMISCOUT[4]See Miscellaneous Outputs Register
EXTOUT[1:0]ITMISCOUT[9:8]See Miscellaneous Outputs Register
nETMWFIREADYITMISCOUT[5]See Miscellaneous Outputs Register
TRIGGERITTRIGGERREQ[0]See Trigger Request Register

Table 3.18. Input signals that the Integration Test Registers can read

SignalRegisterBitRegister description
AFVALIDITATBCTR2[1]See ATB Control Register 2
ATREADYITATBCTR2[0]See ATB Control Register 2
DBGACKITMISCIN[4]See Miscellaneous Inputs Register
ETMCID[31, 0]ITETMIF[11:10]See Processor-ETM Interface Register
ETMDA[31, 0]ITETMIF[7:6]See Processor-ETM Interface Register
ETMDCTL[11, 0]ITETMIF[5:4]See Processor-ETM Interface Register
ETMDD[63, 0]ITETMIF[9:8]See Processor-ETM Interface Register
ETMIA[31, 1]ITETMIF[3:2]See Processor-ETM Interface Register
ETMICTL[13, 0]ITETMIF[1:0]See Processor-ETM Interface Register
ETMWFIPENDINGITMISCIN[5]See Miscellaneous Inputs Register
EVNTBUS[46, 28, 0]ITETMIF[14:12]See Processor-ETM Interface Register
EXTIN[3:0]ITMISCIN[3:0]See Miscellaneous Inputs Register
TRIGGERACKITTRIGGERACK[0]See Trigger Acknowledge Register

Using the Integration Test Registers

The CoreSight ETM‑R4 Integration Manual gives a full description of the use of the Integration Test Registers to check integration. In brief:

When bit[0] of ETMITCTRL is set to 1:

  • Values written to the write-only integration test registers map onto the specified outputs of the macrocell. For example, writing 0x3 to ITMISCOUT[9:8] causes EXTOUT[1:0] to take the value 0x3.

  • Values read from the read-only integration test registers correspond to the values of the specified inputs of the macrocell. For example, if you read ITMISCIN[3:0] you obtain the value of EXTIN[3:0].

When bit[0] of ETMITCTRL is set to 0:

  • Reading an Integration Test Register returns an Unpredictable value.

  • The effect of attempting to write to an Integration Test Register, other than the read-only Integration Test Registers, is Unpredictable.

    Note

    You must not attempt to write to an Integration Test Register unless you have set bit[0] of ETMITCTRL to 1.

See the Embedded Trace Macrocell Architecture Specification for details of ETMITCTRL.

Processor-ETM Interface Register

The ITETMIF characteristics are:

Purpose

Reads the state of the ETM input pins shown in Table 3.19.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The value of the register depends on the signals on the input pins when the register is read.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.12 shows the ITETMIF bit assignments.

Figure 3.12. ITETMIF bit assignments


Table 3.19 lists the ITETMIF bit assignments.

Table 3.19. ITETMIF bit assignments

BitsNameFunction
[31:15]-Reserved. Read undefined.
[14]EVNTBUS[46]Returns the value of the EVNTBUS[46] input pin [a].
[13]EVNTBUS[28]Returns the value of the EVNTBUS[28] input pin [a].
[12]EVNTBUS[0]Returns the value of the EVNTBUS[0] input pin [a].
[11]ETMCID[31]Returns the value of the ETMCID[31] input pin [a].
[10]ETMCID[0]Returns the value of the ETMCID[0] input pin [a].
[9]ETMDD[63]Returns the value of the ETMDD[63] input pin [a].
[8]ETMDD[0]Returns the value of the ETMDD[0] input pin [a].
[7]ETMDA[31]Returns the value of the ETMDA[31] input pin [a].
[6]ETMDA[0]Returns the value of the ETMDA[0] input pin [a].
[5]ETMDCTL[11]Returns the value of the ETMDCTL[11] input pin [a].
[4]ETMDCTL[0]Returns the value of the ETMDCTL[0] input pin [a].
[3]ETMIA[31]Returns the value of the ETMIA[31] input pin [a].
[2]ETMIA[1]Returns the value of the ETMIA[1] input pin [a].
[1]ETMICTL[13]Returns the value of the ETMICTL[13] input pin [a].
[0]ETMICTL[0]Returns the value of the ETMICTL[0] input pin [a].

[a] When a bit is set to 0, the corresponding input pin is LOW.

When a bit is set to 1, the corresponding input pin is HIGH.

The ITETMIF bit values always correspond to the physical state of the input pins.


Miscellaneous Outputs Register

The ITMISCOUT characteristics are:

Purpose

Sets the state of the output pins shown in Table 3.20.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The value of the register sets the signals on the output pins when the register is written.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.13 shows the ITMISCOUT bit assignments.

Figure 3.13. ITMISCOUT bit assignments


Table 3.20 lists the ITMISCOUT bit assignments.

Table 3.20. ITMISCOUT bit assignments

BitsNameFunction
[31:10]-Reserved. Write as zero.
[9:8]EXTOUTDrives the EXTOUT[1:0] output pins[a].
[7:6]-Reserved. Write as zero.
[5]ETMWFIREADY

Drives the nETMWFIREADY output pin[a].

[4]ETMDBGRQDrives the ETMDBGRQ output pin[a].
[3:0]-Reserved. Write as zero.

[a] When an input pin is LOW, the corresponding register bit is 0.

When an input pin is HIGH, the corresponding register bit is 1.

The ITMISCOUT bit values correspond to the physical state of the output pins.


Miscellaneous Inputs Register

The ITMISCIN characteristics are:

Purpose

Reads the state of the input pins shown in Table 3.21.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits depend on the signals on the input pins when the register is read.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.14 shows the ITMISCIN bit assignments.

Figure 3.14. ITMISCIN bit assignments


Table 3.21 lists the ITMISCIN bit assignments.

Table 3.21. ITMISCIN bit assignments

BitsNameFunction
[31:6]-Reserved. Read undefined.
[5]ETMWFIPENDINGReturns the value of the ETMWFIPENDING input pin[a].
[4]DBGACKReturns the value of the DBGACK input pin[a].
[3:0]EXTINReturns the value of the EXTIN[3:0] input pins[a].

[a] When an input pin is LOW, the corresponding register bit is 0.

When an input pin is HIGH, the corresponding register bit is 1.

The ITMISCIN bit values always correspond to the physical state of the input pins.


Trigger Acknowledge Register

The ITTRIGGERACK characteristics are:

Purpose

Reads the state of the TRIGGERACK input pin shown in Table 3.22.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits depend on the signal on the input pin when the register is read.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.15 shows the ITTRIGGERACK bit assignments.

Figure 3.15. ITTRIGGERACK bit assignments


Table 3.22 lists the ITTRIGGERACK bit assignments.

Table 3.22. ITTRIGGERACK bit assignments

BitsNameFunction
[31:1]-Reserved. Read undefined.
[0]TRIGGERACKReturns the value of the TRIGGERACK input pin[a].

[a] When the TRIGGERACK input pin is LOW, the register bit is 0.

When the TRIGGERACK input pin is HIGH, the register bit is 1.

The ITTRIGGERACK bit value always corresponds to the physical state of the input pin.


Trigger Request Register

The ITTRIGGERREQ characteristics are:

Purpose

Sets the TRIGGER output pin shown in Table 3.23.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits set the signals on the output pin when the register is written.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.16 shows the ITTRIGGERREQ bit assignments.

Figure 3.16. ITTRIGGERREQ bit assignments


Table 3.23 lists the ITTRIGGERREQ bit assignments.

Table 3.23. ITTRIGGERREQ bit assignments

BitsNameFunction
[31:1]-Reserved. Write as zero.
[0]TRIGGERDrives the TRIGGER output pin[a].

[a] When the ITTRIGGERREQ register bit is set to 0, the TRIGGER output pin is LOW.

When the ITTRIGGERREQ register bit is set to 1, the TRIGGER output pin is HIGH.

The ITTRIGGERREQ bit values always correspond to the physical state of the output pins.


ATB Data Register 0

The ITATBDATA0 characteristics are:

Purpose

Sets the state of the ATDATA output pins shown in Table 3.24.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits set the signals on the output pins when the register is written.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.17 shows the ITATBDATA0 bit assignments.

Figure 3.17. ITATBDATA0 bit assignments


Table 3.24 lists the ITATBDATA0 bit assignments.

Table 3.24. ITATBDATA0 bit assignments

BitsNameFunction
[31:5]-Reserved. Write as zero.
[4:0]ATDATADrives the ATDATA[31, 23, 15, 7, 0] output pins[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The ITATBDATA0 bit values always correspond to the physical state of the output pins.


ATB Control Register 2

The ITATBCTR2 characteristics are:

Purpose

Reads the state of the AFVALID and ATREADY input pins from the ATB bus, as shown in Table 3.25.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits depend on the signals on the input pins when the register is read.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.18 shows the ITATBCTR2 bit assignments.

Figure 3.18. ITATBCTR2 bit assignments


Table 3.25 lists the ITATBCTR2 bit assignments.

Table 3.25. ITATBCTR2 bit assignments

BitsNameFunction
[31:2]-Reserved. Read undefined.
[1]AFVALIDReturns the value of the AFVALID input pin[a].
[0]ATREADYReturns the value of the ATREADY input pin[a].

[a] When an input pin is LOW, the corresponding register bit is 0.

When an input pin is HIGH, the corresponding register bit is 1.

The ITATBCTR2 bit values always correspond to the physical state of the input pins.


ATB Control Register 1

The ITATBCTR1 characteristics are:

Purpose

Sets the state of the ATID output pins shown in Table 3.26.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits set the signals on the output pins when the register is written.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.19 shows the ITATBCTR1 bit assignments.

Figure 3.19. ITATBCTR1 bit assignments


Table 3.26 lists the ITATBCTR1 bit assignments.

Table 3.26. ITATBCTR1 bit assignments

BitsNameFunction
[31:7]-Reserved. Write as zero.
[6:0]ATIDDrives the ATID[6:0] output pins[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The ITATBCTR1 bit values always correspond to the physical state of the output pins.


ATB Control Register 0

The ITATBCTR0 characteristics are:

Purpose

Sets the state of the output pins shown in Table 3.27.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits set the signals on the output pins when the register is written.

Configurations

Always available.

Attributes

See the register summaries in Table 3.1, Table 3.7 and Table 3.18.

Figure 3.20 shows the ITATBCTR0 bit assignments.

Figure 3.20. ITATBCTR0 bit assignments


Table 3.27 lists the ITATBCTR0 bit assignments.

Table 3.27. ITATBCTR0 bit assignments

BitsNameFunction
[31:10]-Reserved. Write as zero.
[9:8]ATBYTESDrives the ATBYTES[1:0] output pins[a].
[7:2]-Reserved. Write as zero.
[1]AFREADYDrives the AFREADY output pin[a].
[0]ATVALIDDrives the ATVALID output pin[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The ITATBCTR0 bit values always correspond to the physical state of the output pins.


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