1.1.1. The CoreSight debug environment

The ETM-R4 is designed for use with CoreSight, an extensible, system-wide debug and trace architecture from ARM. See the CoreSight Design Kit R4 Integration Manual for more information about how to use the ETM-R4 in a full CoreSight system. See the CoreSight ETM-R4 Integration Manual for an example of how to use the ETM-R4 in a simple trace system.

A software debugger provides the user interface to the ETM-R4. You can use this interface to:

A CoreSight system can provide memory mapped access from the processor to its own debug and trace components.

The ETM-R4 outputs its trace stream to the AMBA 3 ATB interface. The CoreSight infrastructure provides the following options:

The debugger extracts the captured trace information from the TPA or ETB and decompresses it to provide full disassembly, with symbols, of the code that was executed. The trace information generated by the ETM-R4 gives the debugger the capability to link this data back to the original high-level source code, to provide a visualization of how the code was executed on the Cortex-R4 processor.

Figure 1.1 shows how the ETM-R4 fits into a CoreSight debug environment to provide full trace capabilities in a single processor system. The external debug software configures the trace and debug components through the DAP. The ROM table contains a unique identification code for the SoC and the base addresses of the components connected to the debug APB. The trace stream from the ETM-R4 is replicated to provide on-chip storage using the CoreSight ETB or output off-chip using the TPIU. Cross-triggering operates through the CTIs and the cross-trigger matrix.

Figure 1.1. ETM-R4 system diagram


Note

In Figure 1.1, the arrows on the thick lines show the transaction direction on busses, from master to slave port. Each bus contains individual signals that go from master to slave and other signals that go from slave to master.

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